clockrun.rpt

关于自动打铃器的程序设计。应该还是不错的哦！~

-- Node name is 'secldis2' 
-- Equation name is 'secldis2', type is output 
secldis2 =  seclow2;

-- Node name is 'secldis3' 
-- Equation name is 'secldis3', type is output 
secldis3 =  seclow3;

-- Node name is ':46' = 'seclow0' 
-- Equation name is 'seclow0', location is LC5_B23, type is buried.
seclow0  = DFFE(!seclow0, GLOBAL( clk), !(GLOBAL( settime) & !seclset0), !(GLOBAL( settime) &  seclset0),  VCC);

-- Node name is ':45' = 'seclow1' 
-- Equation name is 'seclow1', location is LC7_B23, type is buried.
seclow1  = DFFE( _EQ018, GLOBAL( clk), !(GLOBAL( settime) & !seclset1), !(GLOBAL( settime) &  seclset1),  VCC);
  _EQ018 = !_LC4_B23 & !seclow0 &  seclow1
         # !_LC4_B23 &  seclow0 & !seclow1;

-- Node name is ':44' = 'seclow2' 
-- Equation name is 'seclow2', location is LC1_B23, type is buried.
seclow2  = DFFE( _EQ019, GLOBAL( clk), !(GLOBAL( settime) & !seclset2), !(GLOBAL( settime) &  seclset2),  VCC);
  _EQ019 = !_LC2_B23 & !_LC4_B23 &  seclow2
         #  _LC2_B23 & !_LC4_B23 & !seclow2;

-- Node name is ':43' = 'seclow3' 
-- Equation name is 'seclow3', location is LC3_B23, type is buried.
seclow3  = DFFE( _EQ020, GLOBAL( clk), !(GLOBAL( settime) & !seclset3), !(GLOBAL( settime) &  seclset3),  VCC);
  _EQ020 = !_LC4_B23 & !_LC6_B23 &  seclow3
         # !_LC4_B23 &  _LC6_B23 & !seclow3;

-- Node name is '|LPM_ADD_SUB:365|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A6', type is buried 
!_LC5_A6 = _LC5_A6~NOT;
_LC5_A6~NOT = LCELL( _EQ021);
  _EQ021 = !hourlow1
         # !hourlow0;

-- Node name is '|LPM_ADD_SUB:563|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A18', type is buried 
_LC5_A18 = LCELL( _EQ022);
  _EQ022 =  minlow0 &  minlow1;

-- Node name is '|LPM_ADD_SUB:563|addcore:adder|:77' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_A18', type is buried 
_LC7_A18 = LCELL( _EQ023);
  _EQ023 = !minlow1 &  minlow3
         # !minlow0 &  minlow3
         # !minlow2 &  minlow3
         #  minlow0 &  minlow1 &  minlow2 & !minlow3;

-- Node name is '|LPM_ADD_SUB:838|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B23', type is buried 
_LC2_B23 = LCELL( _EQ024);
  _EQ024 =  seclow0 &  seclow1;

-- Node name is '|LPM_ADD_SUB:838|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B23', type is buried 
_LC6_B23 = LCELL( _EQ025);
  _EQ025 =  seclow0 &  seclow1 &  seclow2;

-- Node name is '~219~1' 
-- Equation name is '~219~1', location is LC8_A21, type is buried.
-- synthesized logic cell 
_LC8_A21 = LCELL( _EQ026);
  _EQ026 =  _LC2_A18 &  minhigh0 & !minhigh1 & !minhigh2;

-- Node name is '~219~2' 
-- Equation name is '~219~2', location is LC2_A19, type is buried.
-- synthesized logic cell 
_LC2_A19 = LCELL( _EQ027);
  _EQ027 =  _LC3_A16 &  _LC4_B23;

-- Node name is '~219~3' 
-- Equation name is '~219~3', location is LC8_A16, type is buried.
-- synthesized logic cell 
_LC8_A16 = LCELL( _EQ028);
  _EQ028 =  _LC1_A24 &  _LC2_A18 &  _LC3_A16 &  _LC4_B23;

-- Node name is '~219~4' 
-- Equation name is '~219~4', location is LC3_A2, type is buried.
-- synthesized logic cell 
_LC3_A2  = LCELL( _EQ029);
  _EQ029 =  _LC5_A6 &  _LC8_A16;

-- Node name is '~219~5' 
-- Equation name is '~219~5', location is LC7_A2, type is buried.
-- synthesized logic cell 
_LC7_A2  = LCELL( _EQ030);
  _EQ030 =  hourlow2 & !hourlow3 &  _LC5_A6 &  _LC8_A16;

-- Node name is ':219' 
-- Equation name is '_LC4_B23', type is buried 
_LC4_B23 = LCELL( _EQ031);
  _EQ031 =  seclow0 & !seclow1 & !seclow2 &  seclow3;

-- Node name is ':235' 
-- Equation name is '_LC3_A16', type is buried 
_LC3_A16 = LCELL( _EQ032);
  _EQ032 =  sechigh0 & !sechigh1 &  sechigh2;

-- Node name is ':251' 
-- Equation name is '_LC2_A18', type is buried 
_LC2_A18 = LCELL( _EQ033);
  _EQ033 =  minlow0 & !minlow1 & !minlow2 &  minlow3;

-- Node name is '~292~1' 
-- Equation name is '~292~1', location is LC5_A12, type is buried.
-- synthesized logic cell 
_LC5_A12 = LCELL( _EQ034);
  _EQ034 =  hourlow0 & !hourlow1;

-- Node name is ':292' 
-- Equation name is '_LC3_A6', type is buried 
_LC3_A6  = LCELL( _EQ035);
  _EQ035 =  hourlow0 & !hourlow1 & !hourlow2 &  hourlow3;

-- Node name is '~311~1' 
-- Equation name is '~311~1', location is LC2_A2, type is buried.
-- synthesized logic cell 
_LC2_A2  = LCELL( _EQ036);
  _EQ036 =  hourlow2
         #  hourhigh0
         # !hourhigh1;

-- Node name is '~507~1' 
-- Equation name is '~507~1', location is LC4_A2, type is buried.
-- synthesized logic cell 
_LC4_A2  = LCELL( _EQ037);
  _EQ037 =  hourlow3 & !_LC3_A6
         # !_LC3_A6 & !_LC5_A6
         #  _LC2_A2 & !_LC3_A6;

-- Node name is '~513~1' 
-- Equation name is '~513~1', location is LC1_A24, type is buried.
-- synthesized logic cell 
_LC1_A24 = LCELL( _EQ038);
  _EQ038 =  _LC4_A2 &  minhigh0 & !minhigh1 &  minhigh2;

-- Node name is ':609' 
-- Equation name is '_LC5_A21', type is buried 
_LC5_A21 = LCELL( _EQ039);
  _EQ039 =  _LC2_A18 &  minhigh0 &  minhigh1 & !minhigh2
         # !minhigh0 &  minhigh2
         # !_LC2_A18 &  minhigh2;

-- Node name is '~610~1' 
-- Equation name is '~610~1', location is LC4_A21, type is buried.
-- synthesized logic cell 
_LC4_A21 = LCELL( _EQ040);
  _EQ040 =  _LC2_A18 & !minhigh2
         #  _LC2_A18 &  minhigh1
         #  _LC2_A18 & !minhigh0;

-- Node name is ':726' 
-- Equation name is '_LC8_A18', type is buried 
_LC8_A18 = LCELL( _EQ041);
  _EQ041 = !_LC2_A18 &  _LC3_A16 &  _LC7_A18
         # !_LC3_A16 &  minlow3;

-- Node name is ':732' 
-- Equation name is '_LC4_A18', type is buried 
_LC4_A18 = LCELL( _EQ042);
  _EQ042 = !_LC2_A18 & !_LC5_A18 &  minlow2
         # !_LC2_A18 &  _LC3_A16 &  _LC5_A18 & !minlow2
         # !_LC3_A16 &  minlow2;

-- Node name is ':738' 
-- Equation name is '_LC3_A18', type is buried 
_LC3_A18 = LCELL( _EQ043);
  _EQ043 = !_LC2_A18 & !minlow0 &  minlow1
         # !_LC2_A18 &  _LC3_A16 &  minlow0 & !minlow1
         # !_LC3_A16 &  minlow1;

-- Node name is ':750' 
-- Equation name is '_LC1_A19', type is buried 
_LC1_A19 = LCELL( _EQ044);
  _EQ044 =  _LC3_A16 &  _LC5_A21
         # !_LC3_A16 &  minhigh2;

-- Node name is ':884' 
-- Equation name is '_LC7_A16', type is buried 
_LC7_A16 = LCELL( _EQ045);
  _EQ045 =  _LC4_B23 &  sechigh0 &  sechigh1 & !sechigh2
         # !sechigh0 &  sechigh2
         # !_LC4_B23 &  sechigh2;

-- Node name is ':890' 
-- Equation name is '_LC6_A16', type is buried 
_LC6_A16 = LCELL( _EQ046);
  _EQ046 = !_LC4_B23 &  sechigh1
         # !_LC3_A16 & !sechigh0 &  sechigh1
         # !_LC3_A16 &  _LC4_B23 &  sechigh0 & !sechigh1;

-- Node name is '~932~1' 
-- Equation name is '~932~1', location is LC6_A21, type is buried.
-- synthesized logic cell 
_LC6_A21 = LCELL( _EQ047);
  _EQ047 =  _LC4_A21 & !minhigh0 &  minhigh1
         #  _LC1_A21 &  minhigh1;

-- Node name is '~938~1' 
-- Equation name is '~938~1', location is LC1_A21, type is buried.
-- synthesized logic cell 
!_LC1_A21 = _LC1_A21~NOT;
_LC1_A21~NOT = LCELL( _EQ048);
  _EQ048 =  _LC2_A18 &  _LC3_A16 &  _LC4_B23;

-- Node name is '~944~1' 
-- Equation name is '~944~1', location is LC8_A2, type is buried.
-- synthesized logic cell 
_LC8_A2  = LCELL( _EQ049);
  _EQ049 = !hourlow2 &  _LC1_A24
         #  _LC1_A24 & !_LC5_A6
         #  _LC3_A21;

-- Node name is '~950~1' 
-- Equation name is '~950~1', location is LC5_A2, type is buried.
-- synthesized logic cell 
_LC5_A2  = LCELL( _EQ050);
  _EQ050 =  _LC1_A24 & !_LC5_A6
         #  _LC3_A21;

-- Node name is '~956~1' 
-- Equation name is '~956~1', location is LC7_A12, type is buried.
-- synthesized logic cell 
_LC7_A12 = LCELL( _EQ051);
  _EQ051 = !hourlow0 &  hourlow1 &  _LC1_A24
         #  hourlow1 &  _LC3_A21;

-- Node name is '~962~1' 
-- Equation name is '~962~1', location is LC3_A21, type is buried.
-- synthesized logic cell 
!_LC3_A21 = _LC3_A21~NOT;
_LC3_A21~NOT = LCELL( _EQ052);
  _EQ052 = !_LC1_A21 &  minhigh0 & !minhigh1 &  minhigh2;

-- Node name is '~968~1' 
-- Equation name is '~968~1', location is LC1_A12, type is buried.
-- synthesized logic cell 
_LC1_A12 = LCELL( _EQ053);
  _EQ053 =  _LC4_A2
         # !hourhigh0 &  _LC3_A6
         #  _LC3_A21;



Project Information        e:\pc-2lab2\max2work\vhdlwork\autoring\clockrun.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 18,380K