ringup.rpt

关于自动打铃器的程序设计。应该还是不错的哦！~

sechdis0 : INPUT;
sechdis1 : INPUT;
sechdis2 : INPUT;
secldis0 : INPUT;
secldis1 : INPUT;
secldis2 : INPUT;
secldis3 : INPUT;

-- Node name is 'alarm' 
-- Equation name is 'alarm', type is output 
alarm    =  _LC4_E29;

-- Node name is '|LPM_ADD_SUB:174|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_E19', type is buried 
!_LC3_E19 = _LC3_E19~NOT;
_LC3_E19~NOT = LCELL( _EQ001);
  _EQ001 = !_LC7_E19 & !secldis2
         # !secldis1 & !secldis2
         # !_LC7_E19 & !secldis1
         # !_LC8_E19 & !secldis2
         # !_LC7_E19 & !_LC8_E19;

-- Node name is '|LPM_ADD_SUB:174|addcore:adder|:115' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC1_E19', type is buried 
_LC1_E19 = LCELL( _EQ002);
  _EQ002 = !_LC8_E19 &  secldis1
         #  _LC8_E19 & !secldis1;

-- Node name is '|LPM_ADD_SUB:174|addcore:adder|:116' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC2_E19', type is buried 
_LC2_E19 = LCELL( _EQ003);
  _EQ003 = !_LC7_E19 &  _LC8_E19 &  secldis1 & !secldis2
         #  _LC7_E19 & !secldis1 & !secldis2
         #  _LC7_E19 & !_LC8_E19 & !secldis2
         #  _LC7_E19 &  _LC8_E19 &  secldis1 &  secldis2
         # !_LC7_E19 & !secldis1 &  secldis2
         # !_LC7_E19 & !_LC8_E19 &  secldis2;

-- Node name is '|LPM_ADD_SUB:174|addcore:adder|:117' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC6_E29', type is buried 
_LC6_E29 = LCELL( _EQ004);
  _EQ004 =  _LC3_E19 & !_LC3_E29 & !secldis3
         # !_LC3_E19 &  _LC3_E29 & !secldis3
         #  _LC3_E19 &  _LC3_E29 &  secldis3
         # !_LC3_E19 & !_LC3_E29 &  secldis3;

-- Node name is '|LPM_MULT:161|multcore:mult_core|:1378' from file "multcore.tdf" line 701, column 38
-- Equation name is '_LC3_E29', type is buried 
!_LC3_E29 = _LC3_E29~NOT;
_LC3_E29~NOT = LCELL( _EQ005);
  _EQ005 = !sechdis0 & !sechdis2
         #  sechdis0 &  sechdis2;

-- Node name is '|LPM_MULT:161|multcore:mult_core|:1402' from file "multcore.tdf" line 702, column 38
-- Equation name is '_LC8_E19', type is buried 
!_LC8_E19 = _LC8_E19~NOT;
_LC8_E19~NOT = LCELL(!sechdis0);

-- Node name is '|LPM_MULT:161|multcore:mult_core|:1405' from file "multcore.tdf" line 702, column 38
-- Equation name is '_LC7_E19', type is buried 
!_LC7_E19 = _LC7_E19~NOT;
_LC7_E19~NOT = LCELL(!sechdis1);

-- Node name is '~256~1' 
-- Equation name is '~256~1', location is LC5_E19, type is buried.
-- synthesized logic cell 
_LC5_E19 = LCELL( _EQ006);
  _EQ006 = !minldis0 & !sechdis1 & !sechdis2;

-- Node name is '~256~2' 
-- Equation name is '~256~2', location is LC6_E19, type is buried.
-- synthesized logic cell 
_LC6_E19 = LCELL( _EQ007);
  _EQ007 =  _LC5_E19 & !minldis1 & !minldis2 & !minldis3;

-- Node name is '~256~3' 
-- Equation name is '~256~3', location is LC4_E19, type is buried.
-- synthesized logic cell 
_LC4_E19 = LCELL( _EQ008);
  _EQ008 =  _LC6_E19 & !minhdis0 & !minhdis1 & !minhdis2;

-- Node name is '~256~4' 
-- Equation name is '~256~4', location is LC1_E29, type is buried.
-- synthesized logic cell 
_LC1_E29 = LCELL( _EQ009);
  _EQ009 = !hourldis0 &  hourldis1 &  hourldis2 &  _LC4_E19;

-- Node name is ':256' 
-- Equation name is '_LC2_E29', type is buried 
_LC2_E29 = LCELL( _EQ010);
  _EQ010 = !hourhdis0 & !hourhdis1 & !hourldis3 &  _LC1_E29;

-- Node name is '~996~1' 
-- Equation name is '~996~1', location is LC7_E29, type is buried.
-- synthesized logic cell 
_LC7_E29 = LCELL( _EQ011);
  _EQ011 =  _LC1_E19 & !_LC6_E29 &  secldis0
         # !_LC1_E19 & !_LC6_E29 & !secldis0
         # !_LC2_E19;

-- Node name is '~1010~1' 
-- Equation name is '~1010~1', location is LC5_E29, type is buried.
-- synthesized logic cell 
_LC5_E29 = LCELL( _EQ012);
  _EQ012 = !_LC3_E29 & !secldis3
         # !_LC3_E19 & !_LC3_E29
         # !_LC3_E19 & !secldis3;

-- Node name is ':1010' 
-- Equation name is '_LC8_E29', type is buried 
_LC8_E29 = LCELL( _EQ013);
  _EQ013 =  _LC2_E29 &  _LC5_E29 &  _LC7_E29;

-- Node name is ':1015' 
-- Equation name is '_LC4_E29', type is buried 
_LC4_E29 = LCELL( _EQ014);
  _EQ014 = !_LC2_E29 &  _LC4_E29 & !reset
         #  _LC8_E29 & !reset;



Project Information                                 d:\eda\autoring\ringup.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 26,872K