📄 ringup.rpt
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Total output pins required: 1
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 16
Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 6/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 16/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 16/0
Device-Specific Information: d:\eda\autoring\ringup.rpt
ringup
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
184 - - - -- INPUT ^ 0 0 0 1 hourhdis0
79 - - - -- INPUT ^ 0 0 0 1 hourhdis1
40 - - E -- INPUT ^ 0 0 0 1 hourldis0
69 - - - 23 INPUT ^ 0 0 0 1 hourldis1
119 - - E -- INPUT ^ 0 0 0 1 hourldis2
39 - - E -- INPUT ^ 0 0 0 1 hourldis3
41 - - E -- INPUT ^ 0 0 0 1 minhdis0
122 - - E -- INPUT ^ 0 0 0 1 minhdis1
64 - - - 26 INPUT ^ 0 0 0 1 minhdis2
183 - - - -- INPUT ^ 0 0 0 1 minldis0
203 - - - 32 INPUT ^ 0 0 0 1 minldis1
196 - - - 27 INPUT ^ 0 0 0 1 minldis2
121 - - E -- INPUT ^ 0 0 0 1 minldis3
182 - - - -- INPUT ^ 0 0 0 1 reset
80 - - - -- INPUT ^ 0 0 0 2 sechdis0
120 - - E -- INPUT ^ 0 0 0 2 sechdis1
78 - - - -- INPUT ^ 0 0 0 2 sechdis2
36 - - E -- INPUT ^ 0 0 0 1 secldis0
197 - - - 28 INPUT ^ 0 0 0 3 secldis1
61 - - - 29 INPUT ^ 0 0 0 2 secldis2
37 - - E -- INPUT ^ 0 0 0 2 secldis3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\eda\autoring\ringup.rpt
ringup
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
38 - - E -- OUTPUT 0 1 0 0 alarm
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\eda\autoring\ringup.rpt
ringup
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - E 19 OR2 ! 2 2 0 2 |LPM_ADD_SUB:174|addcore:adder|pcarry2
- 1 - E 19 OR2 1 1 0 1 |LPM_ADD_SUB:174|addcore:adder|:115
- 2 - E 19 OR2 2 2 0 1 |LPM_ADD_SUB:174|addcore:adder|:116
- 6 - E 29 OR2 1 2 0 1 |LPM_ADD_SUB:174|addcore:adder|:117
- 3 - E 29 OR2 ! 2 0 0 2 |LPM_MULT:161|multcore:mult_core|:1378
- 8 - E 19 AND2 ! 1 0 0 3 |LPM_MULT:161|multcore:mult_core|:1402
- 7 - E 19 AND2 ! 1 0 0 2 |LPM_MULT:161|multcore:mult_core|:1405
- 5 - E 19 AND2 s 3 0 0 1 ~256~1
- 6 - E 19 AND2 s 3 1 0 1 ~256~2
- 4 - E 19 AND2 s 3 1 0 1 ~256~3
- 1 - E 29 AND2 s 3 1 0 1 ~256~4
- 2 - E 29 AND2 3 1 0 2 :256
- 7 - E 29 OR2 s 1 3 0 1 ~996~1
- 5 - E 29 OR2 s 1 2 0 1 ~1010~1
- 8 - E 29 AND2 0 3 0 1 :1010
- 4 - E 29 OR2 1 2 1 0 :1015
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\eda\autoring\ringup.rpt
ringup
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 10/144( 6%) 0/ 72( 0%) 10/ 72( 13%) 9/16( 56%) 1/16( 6%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
27: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
29: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\eda\autoring\ringup.rpt
ringup
** EQUATIONS **
hourhdis0 : INPUT;
hourhdis1 : INPUT;
hourldis0 : INPUT;
hourldis1 : INPUT;
hourldis2 : INPUT;
hourldis3 : INPUT;
minhdis0 : INPUT;
minhdis1 : INPUT;
minhdis2 : INPUT;
minldis0 : INPUT;
minldis1 : INPUT;
minldis2 : INPUT;
minldis3 : INPUT;
reset : INPUT;
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