timeset.rpt

关于自动打铃器的程序设计。应该还是不错的哦！~

-- Node name is ':41' = 'sechigh1' 
-- Equation name is 'sechigh1', location is LC4_C27, type is buried.
sechigh1 = DFFE( _EQ016, GLOBAL( keyup), GLOBAL(!reset),  VCC,  VCC);
  _EQ016 = !sechigh0 &  sechigh1
         #  _LC8_D33 &  sechigh1
         # !_LC8_D33 &  sechigh0 & !sechigh1;

-- Node name is ':40' = 'sechigh2' 
-- Equation name is 'sechigh2', location is LC2_C27, type is buried.
sechigh2 = DFFE( _EQ017, GLOBAL( keyup), GLOBAL(!reset),  VCC,  VCC);
  _EQ017 = !sechigh1 &  sechigh2
         # !sechigh0 &  sechigh2
         #  _LC8_D33 &  sechigh2
         # !_LC8_D33 &  sechigh0 &  sechigh1 & !sechigh2;

-- Node name is 'sechset0' 
-- Equation name is 'sechset0', type is output 
sechset0 =  sechigh0;

-- Node name is 'sechset1' 
-- Equation name is 'sechset1', type is output 
sechset1 =  sechigh1;

-- Node name is 'sechset2' 
-- Equation name is 'sechset2', type is output 
sechset2 =  sechigh2;

-- Node name is ':46' = 'seclow0' 
-- Equation name is 'seclow0', location is LC7_D33, type is buried.
seclow0  = DFFE( _EQ018, GLOBAL( keyup), GLOBAL(!reset),  VCC,  VCC);
  _EQ018 =  _LC1_D33 &  seclow0
         # !_LC1_D33 & !seclow0;

-- Node name is ':45' = 'seclow1' 
-- Equation name is 'seclow1', location is LC6_D33, type is buried.
seclow1  = DFFE( _EQ019, GLOBAL( keyup), GLOBAL(!reset),  VCC,  VCC);
  _EQ019 = !seclow0 &  seclow1
         #  _LC1_D33 &  seclow1
         # !_LC1_D33 &  seclow0 & !seclow1;

-- Node name is ':44' = 'seclow2' 
-- Equation name is 'seclow2', location is LC5_D33, type is buried.
seclow2  = DFFE( _EQ020, GLOBAL( keyup), GLOBAL(!reset),  VCC,  VCC);
  _EQ020 = !seclow1 &  seclow2
         # !seclow0 &  seclow2
         #  _LC1_D33 &  seclow2
         # !_LC1_D33 &  seclow0 &  seclow1 & !seclow2;

-- Node name is ':43' = 'seclow3' 
-- Equation name is 'seclow3', location is LC3_D33, type is buried.
seclow3  = DFFE( _EQ021, GLOBAL( keyup), GLOBAL(!reset),  VCC,  VCC);
  _EQ021 = !_LC2_D33 &  seclow3
         # !seclow2 &  seclow3
         #  _LC1_D33 &  seclow3
         # !_LC1_D33 &  _LC2_D33 &  seclow2 & !seclow3;

-- Node name is 'seclset0' 
-- Equation name is 'seclset0', type is output 
seclset0 =  seclow0;

-- Node name is 'seclset1' 
-- Equation name is 'seclset1', type is output 
seclset1 =  seclow1;

-- Node name is 'seclset2' 
-- Equation name is 'seclset2', type is output 
seclset2 =  seclow2;

-- Node name is 'seclset3' 
-- Equation name is 'seclset3', type is output 
seclset3 =  seclow3;

-- Node name is ':26' = 'setmark' 
-- Equation name is 'setmark', location is LC4_E29, type is buried.
setmark  = DFFE(!setmark, GLOBAL( begend), GLOBAL(!reset),  VCC,  VCC);

-- Node name is 'settime' 
-- Equation name is 'settime', type is output 
settime  =  setmark;

-- Node name is '|LPM_ADD_SUB:247|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_D19', type is buried 
_LC7_D19 = LCELL( _EQ022);
  _EQ022 =  hourlow0 &  hourlow1;

-- Node name is '|LPM_ADD_SUB:300|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_D27', type is buried 
_LC8_D27 = LCELL( _EQ023);
  _EQ023 =  minlow0 &  minlow1;

-- Node name is '|LPM_ADD_SUB:353|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_D33', type is buried 
_LC2_D33 = LCELL( _EQ024);
  _EQ024 =  seclow0 &  seclow1;

-- Node name is '~453~1' 
-- Equation name is '~453~1', location is LC1_D19, type is buried.
-- synthesized logic cell 
!_LC1_D19 = _LC1_D19~NOT;
_LC1_D19~NOT = LCELL( _EQ025);
  _EQ025 = !adjsta~5 & !adjsta~6 & !adjsta~7;

-- Node name is '~453~2' 
-- Equation name is '~453~2', location is LC1_D33, type is buried.
-- synthesized logic cell 
!_LC1_D33 = _LC1_D33~NOT;
_LC1_D33~NOT = LCELL( _EQ026);
  _EQ026 =  adjsta~2 & !adjsta~3 & !adjsta~4 & !_LC1_D19;

-- Node name is '~516~1' 
-- Equation name is '~516~1', location is LC8_D33, type is buried.
-- synthesized logic cell 
!_LC8_D33 = _LC8_D33~NOT;
_LC8_D33~NOT = LCELL( _EQ027);
  _EQ027 =  adjsta~3 & !adjsta~4 & !_LC1_D19;

-- Node name is '~600~1' 
-- Equation name is '~600~1', location is LC4_D27, type is buried.
-- synthesized logic cell 
!_LC4_D27 = _LC4_D27~NOT;
_LC4_D27~NOT = LCELL( _EQ028);
  _EQ028 =  adjsta~4 & !adjsta~5 & !adjsta~6 & !adjsta~7;

-- Node name is '~663~1' 
-- Equation name is '~663~1', location is LC4_D34, type is buried.
-- synthesized logic cell 
!_LC4_D34 = _LC4_D34~NOT;
_LC4_D34~NOT = LCELL( _EQ029);
  _EQ029 =  adjsta~5 & !adjsta~6 & !adjsta~7;

-- Node name is '~747~1' 
-- Equation name is '~747~1', location is LC5_D19, type is buried.
-- synthesized logic cell 
!_LC5_D19 = _LC5_D19~NOT;
_LC5_D19~NOT = LCELL( _EQ030);
  _EQ030 =  adjsta~6 & !adjsta~7;



Project Information                                    d:\autoring\timeset.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 29,008K