📄 timeset.rpt
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** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
C27 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 1/22( 4%)
D19 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 2/2 1/2 2/22( 9%)
D27 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 2/2 1/2 3/22( 13%)
D28 4/ 8( 50%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
D33 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 2/2 1/2 3/22( 13%)
D34 5/ 8( 62%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 2/22( 9%)
E29 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 0/22( 0%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 4/6 ( 66%)
Total I/O pins used: 21/141 ( 14%)
Total logic cells used: 37/1728 ( 2%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 2.56/4 ( 64%)
Total fan-in: 95/6912 ( 1%)
Total input pins required: 4
Total input I/O cell registers required: 0
Total output pins required: 21
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 37
Total flipflops required: 28
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 6/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 3/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 8 4 0 0 0 0 8 5 0 0 33/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 11 4 1 0 0 0 8 5 0 0 37/0
Device-Specific Information: d:\autoring\timeset.rpt
timeset
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
80 - - - -- INPUT G ^ 0 0 0 0 begend
79 - - - -- INPUT G ^ 0 0 0 0 enter
183 - - - -- INPUT G ^ 0 0 0 0 keyup
78 - - - -- INPUT G ^ 0 0 0 0 reset
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\autoring\timeset.rpt
timeset
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
28 - - D -- OUTPUT 0 1 0 0 hourhset0
125 - - D -- OUTPUT 0 1 0 0 hourhset1
187 - - - 20 OUTPUT 0 1 0 0 hourlset0
74 - - - 20 OUTPUT 0 1 0 0 hourlset1
27 - - D -- OUTPUT 0 1 0 0 hourlset2
30 - - D -- OUTPUT 0 1 0 0 hourlset3
26 - - D -- OUTPUT 0 1 0 0 minhset0
128 - - D -- OUTPUT 0 1 0 0 minhset1
56 - - - 33 OUTPUT 0 1 0 0 minhset2
62 - - - 28 OUTPUT 0 1 0 0 minlset0
198 - - - 28 OUTPUT 0 1 0 0 minlset1
126 - - D -- OUTPUT 0 1 0 0 minlset2
18 - - C -- OUTPUT 0 1 0 0 minlset3
16 - - C -- OUTPUT 0 1 0 0 sechset0
19 - - C -- OUTPUT 0 1 0 0 sechset1
17 - - C -- OUTPUT 0 1 0 0 sechset2
31 - - D -- OUTPUT 0 1 0 0 seclset0
206 - - - 34 OUTPUT 0 1 0 0 seclset1
29 - - D -- OUTPUT 0 1 0 0 seclset2
127 - - D -- OUTPUT 0 1 0 0 seclset3
38 - - E -- OUTPUT 0 1 0 0 settime
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\autoring\timeset.rpt
timeset
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - D 28 DFFE + 0 0 0 1 adjsta~1
- 4 - D 33 DFFE + 0 1 0 2 adjsta~2
- 1 - D 27 DFFE + 0 1 0 3 adjsta~3
- 2 - D 27 DFFE + 0 1 0 4 adjsta~4
- 3 - D 34 DFFE + 0 1 0 4 adjsta~5
- 8 - D 19 DFFE + 0 1 0 5 adjsta~6
- 1 - D 28 DFFE + 0 2 0 7 adjsta~7
- 7 - D 19 AND2 0 2 0 1 |LPM_ADD_SUB:247|addcore:adder|:59
- 8 - D 27 AND2 0 2 0 1 |LPM_ADD_SUB:300|addcore:adder|:59
- 2 - D 33 AND2 0 2 0 1 |LPM_ADD_SUB:353|addcore:adder|:59
- 4 - E 29 DFFE + 0 0 1 0 setmark (:26)
- 8 - D 28 DFFE + 0 2 1 0 hourhigh1 (:27)
- 4 - D 28 DFFE + 0 1 1 1 hourhigh0 (:28)
- 6 - D 19 DFFE + 0 3 1 0 hourlow3 (:29)
- 3 - D 19 DFFE + 0 3 1 1 hourlow2 (:30)
- 2 - D 19 DFFE + 0 2 1 2 hourlow1 (:31)
- 4 - D 19 DFFE + 0 1 1 3 hourlow0 (:32)
- 5 - D 34 DFFE + 0 3 1 0 minhigh2 (:33)
- 1 - D 34 DFFE + 0 2 1 1 minhigh1 (:34)
- 2 - D 34 DFFE + 0 1 1 2 minhigh0 (:35)
- 3 - D 27 DFFE + 0 3 1 0 minlow3 (:36)
- 5 - D 27 DFFE + 0 3 1 1 minlow2 (:37)
- 7 - D 27 DFFE + 0 2 1 2 minlow1 (:38)
- 6 - D 27 DFFE + 0 1 1 3 minlow0 (:39)
- 2 - C 27 DFFE + 0 3 1 0 sechigh2 (:40)
- 4 - C 27 DFFE + 0 2 1 1 sechigh1 (:41)
- 1 - C 27 DFFE + 0 1 1 2 sechigh0 (:42)
- 3 - D 33 DFFE + 0 3 1 0 seclow3 (:43)
- 5 - D 33 DFFE + 0 3 1 1 seclow2 (:44)
- 6 - D 33 DFFE + 0 2 1 2 seclow1 (:45)
- 7 - D 33 DFFE + 0 1 1 3 seclow0 (:46)
- 1 - D 19 AND2 s ! 0 3 0 2 ~453~1
- 1 - D 33 AND2 s ! 0 4 0 4 ~453~2
- 8 - D 33 AND2 s ! 0 3 0 3 ~516~1
- 4 - D 27 AND2 s ! 0 4 0 4 ~600~1
- 4 - D 34 AND2 s ! 0 3 0 3 ~663~1
- 5 - D 19 AND2 s ! 0 2 0 4 ~747~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\autoring\timeset.rpt
timeset
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 5/ 72( 6%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
D: 10/144( 6%) 0/ 72( 0%) 7/ 72( 9%) 0/16( 0%) 10/16( 62%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 1/ 72( 1%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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