ringup2.rpt

关于自动打铃器的程序设计。应该还是不错的哦！~

_LC1_A24 = LCELL( _EQ009);
  _EQ009 = !hourldis0 & !_LC5_A24 &  _LC7_A24
         # !hourldis0 &  _LC7_A24 & !_LC8_A24;

-- Node name is '~568~1' 
-- Equation name is '~568~1', location is LC5_A33, type is buried.
-- synthesized logic cell 
!_LC5_A33 = _LC5_A33~NOT;
_LC5_A33~NOT = LCELL( _EQ010);
  _EQ010 =  sechdis2
         #  sechdis1;

-- Node name is '~568~2' 
-- Equation name is '~568~2', location is LC1_A26, type is buried.
-- synthesized logic cell 
_LC1_A26 = LCELL( _EQ011);
  _EQ011 =  _LC5_A33 & !minldis0 & !minldis1 & !minldis2;

-- Node name is '~568~3' 
-- Equation name is '~568~3', location is LC4_A24, type is buried.
-- synthesized logic cell 
_LC4_A24 = LCELL( _EQ012);
  _EQ012 =  _LC1_A26 & !minhdis0 & !minhdis1 & !minldis3;

-- Node name is '~568~4' 
-- Equation name is '~568~4', location is LC2_A24, type is buried.
-- synthesized logic cell 
_LC2_A24 = LCELL( _EQ013);
  _EQ013 =  _LC4_A24 & !minhdis2 & !sechdis0 & !secldis3;

-- Node name is '~568~5' 
-- Equation name is '~568~5', location is LC6_A24, type is buried.
-- synthesized logic cell 
_LC6_A24 = LCELL( _EQ014);
  _EQ014 =  _LC1_A26 & !minldis3;

-- Node name is ':568' 
-- Equation name is '_LC3_A29', type is buried 
_LC3_A29 = LCELL( _EQ015);
  _EQ015 =  _LC2_A24 & !secldis0 & !secldis1 & !secldis2;

-- Node name is '~967~1' 
-- Equation name is '~967~1', location is LC2_A35, type is buried.
-- synthesized logic cell 
_LC2_A35 = LCELL( _EQ016);
  _EQ016 = !hourhdis0 &  hourldis3;

-- Node name is '~967~2' 
-- Equation name is '~967~2', location is LC3_A35, type is buried.
-- synthesized logic cell 
!_LC3_A35 = _LC3_A35~NOT;
_LC3_A35~NOT = LCELL( _EQ017);
  _EQ017 =  hourhdis0 & !hourldis0 & !hourldis3
         # !hourhdis0 &  hourldis0 &  hourldis3;

-- Node name is '~967~3' 
-- Equation name is '~967~3', location is LC4_A35, type is buried.
-- synthesized logic cell 
!_LC4_A35 = _LC4_A35~NOT;
_LC4_A35~NOT = LCELL( _EQ018);
  _EQ018 =  _LC2_A35 &  minhdis1 & !minhdis2
         # !_LC3_A35 & !minhdis1 &  minhdis2;

-- Node name is '~967~4' 
-- Equation name is '~967~4', location is LC5_A35, type is buried.
-- synthesized logic cell 
!_LC5_A35 = _LC5_A35~NOT;
_LC5_A35~NOT = LCELL( _EQ019);
  _EQ019 = !hourldis0 & !_LC4_A35 &  minhdis1
         # !_LC4_A35 & !minhdis0;

-- Node name is '~967~5' 
-- Equation name is '~967~5', location is LC6_A35, type is buried.
-- synthesized logic cell 
_LC6_A35 = LCELL( _EQ020);
  _EQ020 = !hourldis3 &  minhdis0 &  minhdis1 & !minhdis2;

-- Node name is '~967~6' 
-- Equation name is '~967~6', location is LC7_A35, type is buried.
-- synthesized logic cell 
!_LC7_A35 = _LC7_A35~NOT;
_LC7_A35~NOT = LCELL( _EQ021);
  _EQ021 =  _LC2_A19 & !_LC5_A35
         #  hourhdis0 &  _LC2_A19 &  _LC6_A35;

-- Node name is '~967~7' 
-- Equation name is '~967~7', location is LC3_A24, type is buried.
-- synthesized logic cell 
_LC3_A24 = LCELL( _EQ022);
  _EQ022 = !hourhdis0 &  hourldis1 &  hourldis2;

-- Node name is '~967~8' 
-- Equation name is '~967~8', location is LC8_A35, type is buried.
-- synthesized logic cell 
!_LC8_A35 = _LC8_A35~NOT;
_LC8_A35~NOT = LCELL( _EQ023);
  _EQ023 = !_LC7_A35
         #  hourldis0 &  _LC3_A24 &  _LC6_A35;

-- Node name is ':967' 
-- Equation name is '_LC1_A35', type is buried 
_LC1_A35 = LCELL( _EQ024);
  _EQ024 = !hourhdis1 &  _LC1_A26 & !_LC8_A35 & !minldis3;

-- Node name is '~1460~1' 
-- Equation name is '~1460~1', location is LC6_A29, type is buried.
-- synthesized logic cell 
_LC6_A29 = LCELL( _EQ025);
  _EQ025 = !_LC3_A33
         #  _LC1_A21 & !secldis0 &  secldis1
         # !_LC1_A21 & !secldis0 & !secldis1
         # !_LC1_A21 &  secldis0 &  secldis1
         #  _LC1_A21 &  secldis0 & !secldis1;

-- Node name is ':1605' 
-- Equation name is '_LC1_A33', type is buried 
_LC1_A33 = LCELL( _EQ026);
  _EQ026 =  _LC6_A33 & !_LC8_A33 &  secldis3
         # !_LC6_A33 &  _LC8_A33 &  secldis3
         #  _LC6_A33 &  _LC8_A33 & !secldis3
         # !_LC6_A33 & !_LC8_A33 & !secldis3
         # !_LC3_A33;

-- Node name is ':1821' 
-- Equation name is '_LC7_A29', type is buried 
_LC7_A29 = LCELL( _EQ027);
  _EQ027 =  _LC1_A33 &  _LC2_A33 & !_LC4_A33
         #  _LC1_A33 &  _LC2_A33 &  _LC6_A29;

-- Node name is '~2515~1' 
-- Equation name is '~2515~1', location is LC4_A33, type is buried.
-- synthesized logic cell 
!_LC4_A33 = _LC4_A33~NOT;
_LC4_A33~NOT = LCELL( _EQ028);
  _EQ028 = !_LC5_A33
         #  secldis3
         #  _LC6_A33
         #  _LC8_A33;

-- Node name is '~2515~2' 
-- Equation name is '~2515~2', location is LC2_A33, type is buried.
-- synthesized logic cell 
_LC2_A33 = LCELL( _EQ029);
  _EQ029 =  _LC5_A33 & !_LC8_A33 & !secldis3
         #  _LC5_A33 & !_LC6_A33 & !_LC8_A33
         #  _LC5_A33 & !_LC6_A33 & !secldis3;

-- Node name is ':2515' 
-- Equation name is '_LC2_A29', type is buried 
_LC2_A29 = LCELL( _EQ030);
  _EQ030 = !_LC1_A29 &  _LC4_A33 & !secldis0
         # !_LC3_A33 &  _LC4_A33;

-- Node name is ':2534' 
-- Equation name is '_LC5_A29', type is buried 
_LC5_A29 = LCELL( _EQ031);
  _EQ031 = !_LC1_A35 &  _LC4_A29
         #  _LC1_A35 &  _LC2_A29
         #  _LC3_A29;

-- Node name is ':2541' 
-- Equation name is '_LC8_A29', type is buried 
_LC8_A29 = LCELL( _EQ032);
  _EQ032 =  _LC1_A24 &  _LC2_A29
         #  _LC1_A24 &  _LC7_A29;

-- Node name is ':2546' 
-- Equation name is '_LC4_A29', type is buried 
_LC4_A29 = LCELL( _EQ033);
  _EQ033 = !_LC1_A24 &  _LC5_A29 & !RESET
         #  _LC8_A29 & !RESET;



Project Information                                    d:\autoring\ringup2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 25,455K