📄 segdis02.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity segdis02 is
port( sclk: in std_logic;
leddis: out std_logic_vector(7 downto 0);
disin: in integer range 0 to 5);
procedure led(number: integer range 0 to 5) is
begin
case number is
when 0=>
leddis<="00111111";
when 1=>
leddis<="00000110";
when 2=>
leddis<="01011011";
when 3=>
leddis<="01001111";
when 4=>
leddis<="01100110";
when 5=>
leddis<="01101101";
end case;
end led;
end segdis02;
architecture segarchi of segdis02 is
begin
scan:
process(sclk)
begin
if (sclk='1' and sclk'event) then
led(disin);
end if;
end process;
end segarchi;
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