📄 display.rpt
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- 3 - A 24 OR2 0 4 0 1 :1493
- 7 - A 24 OR2 4 0 0 1 :1543
- 6 - A 24 AND2 s 3 0 0 2 ~1553~1
- 4 - A 24 OR2 0 4 0 1 :1553
- 2 - A 24 OR2 4 0 0 2 :1585
- 4 - A 23 AND2 3 0 0 1 :1859
- 5 - A 23 OR2 3 0 0 1 :2074
- 2 - A 32 OR2 ! 4 0 0 2 :2344
- 1 - A 32 OR2 ! 4 0 0 2 :2356
- 3 - A 32 AND2 4 0 0 4 :2368
- 7 - A 32 OR2 4 0 0 1 :2431
- 4 - A 22 OR2 4 0 0 1 :2484
- 5 - A 22 OR2 0 4 0 1 :2491
- 8 - A 32 OR2 4 0 0 1 :2541
- 3 - A 22 AND2 s 3 0 0 2 ~2551~1
- 4 - A 32 OR2 0 4 0 1 :2551
- 6 - A 32 OR2 4 0 0 2 :2583
- 1 - A 19 OR2 ! 3 0 0 1 :2837
- 1 - A 26 AND2 3 0 0 5 :2857
- 8 - A 26 OR2 3 0 0 1 :2922
- 3 - A 26 OR2 3 1 0 1 :2980
- 5 - A 26 OR2 s 3 0 0 1 ~3040~1
- 1 - A 23 OR2 3 1 0 1 :3070
- 2 - A 35 OR2 ! 4 0 0 2 :3342
- 4 - A 35 OR2 ! 4 0 0 2 :3354
- 1 - A 35 AND2 4 0 0 6 :3366
- 6 - A 26 OR2 0 3 0 1 :3429
- 1 - A 28 OR2 4 0 0 1 :3482
- 6 - A 22 OR2 0 3 0 1 :3491
- 3 - A 35 OR2 4 0 0 1 :3539
- 2 - A 28 AND2 s 3 0 0 3 ~3549~1
- 2 - A 27 OR2 0 4 0 1 :3549
- 8 - A 35 OR2 4 0 0 2 :3581
- 1 - A 11 AND2 0 3 0 8 :3606
- 3 - A 02 AND2 0 3 0 9 :3616
- 5 - A 02 AND2 0 3 0 17 :3626
- 5 - A 11 OR2 ! 0 3 0 11 :3636
- 6 - A 11 AND2 0 3 0 11 :3646
- 6 - A 02 AND2 0 4 1 0 :3651
- 1 - A 02 OR2 0 4 1 0 :3669
- 2 - A 25 OR2 0 4 0 1 :3709
- 4 - A 26 OR2 s 3 0 0 1 ~3710~1
- 5 - A 35 OR2 s 4 0 0 2 ~3711~1
- 1 - A 25 OR2 s 4 0 0 1 ~3713~1
- 3 - A 30 OR2 3 1 0 1 :3716
- 3 - A 25 OR2 0 4 0 1 :3717
- 5 - A 25 OR2 0 4 0 1 :3718
- 4 - A 25 OR2 s 4 0 0 1 ~3719~1
- 6 - A 25 OR2 1 2 1 0 :3721
- 7 - A 26 OR2 0 4 0 1 :3727
- 5 - A 30 OR2 3 1 0 1 :3734
- 8 - A 25 OR2 0 4 0 1 :3735
- 2 - A 30 OR2 0 4 0 1 :3736
- 7 - A 19 OR2 2 2 1 0 :3739
- 7 - A 35 OR2 s 4 0 0 1 ~3757~1
- 6 - A 35 OR2 s 0 4 0 1 ~3757~2
- 8 - A 22 AND2 s 2 0 0 1 ~3757~3
- 2 - A 22 OR2 s 0 4 0 1 ~3757~4
- 5 - A 32 OR2 s 4 0 0 1 ~3757~5
- 1 - A 36 OR2 s 0 4 0 1 ~3757~6
- 3 - A 36 OR2 s 0 4 0 1 ~3757~7
- 4 - A 36 OR2 s 3 1 0 1 ~3757~8
- 7 - A 30 OR2 s 4 0 0 1 ~3757~9
- 5 - A 36 OR2 s 0 4 0 1 ~3757~10
- 6 - A 36 OR2 s 0 4 0 1 ~3757~11
- 2 - A 36 OR2 1 2 1 0 :3757
- 7 - A 22 OR2 0 4 0 1 :3763
- 1 - A 30 OR2 3 1 0 1 :3770
- 1 - A 22 OR2 0 4 0 1 :3771
- 8 - A 19 OR2 0 4 0 1 :3772
- 2 - A 19 OR2 2 2 1 0 :3775
- 3 - A 19 OR2 0 3 0 1 :3781
- 6 - A 30 OR2 3 1 0 1 :3788
- 4 - A 19 OR2 0 4 0 1 :3789
- 6 - A 19 OR2 0 4 0 1 :3790
- 5 - A 19 OR2 2 2 1 0 :3793
- 2 - A 26 OR2 0 4 0 1 :3799
- 4 - A 02 OR2 3 1 0 1 :3806
- 2 - A 02 OR2 0 4 0 1 :3807
- 8 - A 02 OR2 0 4 0 1 :3808
- 7 - A 02 OR2 0 2 1 0 :3811
- 2 - A 23 OR2 0 4 0 1 :3817
- 3 - A 23 OR2 0 4 0 1 :3820
- 7 - A 23 OR2 0 4 0 1 :3823
- 8 - A 23 OR2 0 4 0 1 :3826
- 6 - A 23 OR2 2 2 1 0 :3829
- 7 - A 11 OR2 0 4 1 1 :3883
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information:e:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\display.rpt
display
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 35/144( 24%) 2/ 72( 2%) 29/ 72( 40%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
27: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
29: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
34: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
35: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
36: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\display.rpt
display
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 sclk
Device-Specific Information:e:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\display.rpt
display
** EQUATIONS **
hourhdis0 : INPUT;
hourhdis1 : INPUT;
hourldis0 : INPUT;
hourldis1 : INPUT;
hourldis2 : INPUT;
hourldis3 : INPUT;
minhdis0 : INPUT;
minhdis1 : INPUT;
minhdis2 : INPUT;
minldis0 : INPUT;
minldis1 : INPUT;
minldis2 : INPUT;
minldis3 : INPUT;
reset : INPUT;
sclk : INPUT;
sechdis0 : INPUT;
sechdis1 : INPUT;
sechdis2 : INPUT;
secldis0 : INPUT;
secldis1 : INPUT;
secldis2 : INPUT;
secldis3 : INPUT;
-- Node name is 'addsel0'
-- Equation name is 'addsel0', type is output
addsel0 = !_LC7_A11;
-- Node name is 'addsel1'
-- Equation name is 'addsel1', type is output
addsel1 = _LC1_A2;
-- Node name is 'addsel2'
-- Equation name is 'addsel2', type is output
addsel2 = _LC6_A2;
-- Node name is ':39' = 'cursta0'
-- Equation name is 'cursta0', location is LC4_A11, type is buried.
cursta0 = DFFE( _LC7_A11, GLOBAL( sclk), VCC, VCC, !_LC8_A11);
-- Node name is ':38' = 'cursta1'
-- Equation name is 'cursta1', location is LC2_A11, type is buried.
cursta1 = DFFE( _EQ001, GLOBAL( sclk), VCC, VCC, !_LC8_A11);
_EQ001 = _LC5_A11 & !_LC6_A11
# _LC5_A2 & !_LC6_A11;
-- Node name is ':37' = 'cursta2'
-- Equation name is 'cursta2', location is LC3_A11, type is buried.
cursta2 = DFFE( _EQ002, GLOBAL( sclk), VCC, VCC, !_LC8_A11);
_EQ002 = !cursta0 & !cursta1 & cursta2
# cursta0 & cursta1 & !cursta2;
-- Node name is 'reset~1'
-- Equation name is 'reset~1', location is LC8_A11, type is buried.
-- synthesized logic cell
!_LC8_A11 = _LC8_A11~NOT;
_LC8_A11~NOT = LCELL(!reset);
-- Node name is 'secdis0'
-- Equation name is 'secdis0', type is output
secdis0 = _LC6_A23;
-- Node name is 'secdis1'
-- Equation name is 'secdis1', type is output
secdis1 = _LC7_A2;
-- Node name is 'secdis2'
-- Equation name is 'secdis2', type is output
secdis2 = _LC5_A19;
-- Node name is 'secdis3'
-- Equation name is 'secdis3', type is output
secdis3 = _LC2_A19;
-- Node name is 'secdis4'
-- Equation name is 'secdis4', type is output
secdis4 = _LC2_A36;
-- Node name is 'secdis5'
-- Equation name is 'secdis5', type is output
secdis5 = _LC7_A19;
-- Node name is 'secdis6'
-- Equation name is 'secdis6', type is output
secdis6 = _LC6_A25;
-- Node name is 'secdis7'
-- Equation name is 'secdis7', type is output
secdis7 = GND;
-- Node name is ':1346'
-- Equation name is '_LC1_A24', type is buried
!_LC1_A24 = _LC1_A24~NOT;
_LC1_A24~NOT = LCELL( _EQ003);
_EQ003 = hourldis3
# hourldis0
# !hourldis1
# hourldis2;
-- Node name is ':1358'
-- Equation name is '_LC5_A24', type is buried
!_LC5_A24 = _LC5_A24~NOT;
_LC5_A24~NOT = LCELL( _EQ004);
_EQ004 = hourldis3
# !hourldis0
# hourldis1
# hourldis2;
-- Node name is ':1370'
-- Equation name is '_LC4_A30', type is buried
_LC4_A30 = LCELL( _EQ005);
_EQ005 = !hourldis0 & !hourldis1 & !hourldis2 & !hourldis3;
-- Node name is ':1433'
-- Equation name is '_LC8_A30', type is buried
_LC8_A30 = LCELL( _EQ006);
_EQ006 = hourldis3
# !hourldis1 & hourldis2
# !hourldis0 & !hourldis1
# !hourldis0 & hourldis2;
-- Node name is ':1486'
-- Equation name is '_LC8_A24', type is buried
_LC8_A24 = LCELL( _EQ007);
_EQ007 = hourldis3
# !hourldis2
# hourldis0 & !hourldis1
# !hourldis0 & hourldis1;
-- Node name is ':1493'
-- Equation name is '_LC3_A24', type is buried
_LC3_A24 = LCELL( _EQ008);
_EQ008 = !_LC5_A24 & _LC8_A24
# !_LC5_A24 & _LC6_A24
# _LC4_A30;
-- Node name is ':1543'
-- Equation name is '_LC7_A24', type is buried
_LC7_A24 = LCELL( _EQ009);
_EQ009 = hourldis3
# !hourldis2
# !hourldis0 & !hourldis1
# hourldis0 & hourldis1;
-- Node name is '~1553~1'
-- Equation name is '~1553~1', location is LC6_A24, type is buried.
-- synthesized logic cell
_LC6_A24 = LCELL( _EQ010);
_EQ010 = hourldis1 & !hourldis2 & !hourldis3;
-- Node name is ':1553'
-- Equation name is '_LC4_A24', type is buried
_LC4_A24 = LCELL( _EQ011);
_EQ011 = _LC6_A24
# _LC7_A24
# !_LC2_A24
# _LC4_A30;
-- Node name is ':1585'
-- Equation name is '_LC2_A24', type is buried
_LC2_A24 = LCELL( _EQ012);
_EQ012 = hourldis3
# hourldis1
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