timer_ring2.rpt

关于自动打铃器的程序设计。应该还是不错的哦！~

-- synthesized logic cell 
_LC2_B1  = LCELL( _EQ012);
  _EQ012 =  _LC4_B1 & !minldis1 & !minldis2 & !minldis3;

-- Node name is '~567~3' 
-- Equation name is '~567~3', location is LC6_B1, type is buried.
-- synthesized logic cell 
_LC6_B1  = LCELL( _EQ013);
  _EQ013 = !sechdis1 & !sechdis2;

-- Node name is '~567~4' 
-- Equation name is '~567~4', location is LC4_B6, type is buried.
-- synthesized logic cell 
_LC4_B6  = LCELL( _EQ014);
  _EQ014 = !minhdis0 & !minhdis1;

-- Node name is '~567~5' 
-- Equation name is '~567~5', location is LC1_B10, type is buried.
-- synthesized logic cell 
_LC1_B10 = LCELL( _EQ015);
  _EQ015 =  _LC4_B6 & !minhdis2 & !secldis0 & !secldis1;

-- Node name is '~567~6' 
-- Equation name is '~567~6', location is LC3_B4, type is buried.
-- synthesized logic cell 
_LC3_B4  = LCELL( _EQ016);
  _EQ016 =  _LC1_B10 & !sechdis0 & !secldis2 & !secldis3;

-- Node name is '~966~1' 
-- Equation name is '~966~1', location is LC4_B12, type is buried.
-- synthesized logic cell 
!_LC4_B12 = _LC4_B12~NOT;
_LC4_B12~NOT = LCELL( _EQ017);
  _EQ017 = !minhdis1
         # !minhdis0
         #  hourldis3
         #  minhdis2;

-- Node name is '~966~2' 
-- Equation name is '~966~2', location is LC3_B6, type is buried.
-- synthesized logic cell 
_LC3_B6  = LCELL( _EQ018);
  _EQ018 = !hourhdis0 &  hourldis1 &  hourldis2;

-- Node name is '~966~3' 
-- Equation name is '~966~3', location is LC3_B12, type is buried.
-- synthesized logic cell 
_LC3_B12 = LCELL( _EQ019);
  _EQ019 = !_LC4_B12
         # !_LC3_B6
         # !hourldis0;

-- Node name is '~966~4' 
-- Equation name is '~966~4', location is LC5_B12, type is buried.
-- synthesized logic cell 
_LC5_B12 = LCELL( _EQ020);
  _EQ020 =  hourhdis0 &  hourldis3
         #  hourhdis0 &  hourldis0
         # !hourhdis0 & !hourldis3
         #  hourldis0 & !hourldis3
         # !hourhdis0 & !hourldis0
         # !hourldis0 &  hourldis3;

-- Node name is '~966~5' 
-- Equation name is '~966~5', location is LC6_B12, type is buried.
-- synthesized logic cell 
!_LC6_B12 = _LC6_B12~NOT;
_LC6_B12~NOT = LCELL( _EQ021);
  _EQ021 =  hourhdis0
         # !hourldis3;

-- Node name is '~966~6' 
-- Equation name is '~966~6', location is LC7_B12, type is buried.
-- synthesized logic cell 
_LC7_B12 = LCELL( _EQ022);
  _EQ022 =  _LC5_B12 & !_LC6_B12
         #  _LC5_B12 &  minhdis2
         #  _LC5_B12 & !minhdis1
         # !_LC6_B12 & !minhdis2
         # !minhdis1 & !minhdis2
         # !_LC6_B12 &  minhdis1
         #  minhdis1 &  minhdis2;

-- Node name is '~966~7' 
-- Equation name is '~966~7', location is LC8_B12, type is buried.
-- synthesized logic cell 
_LC8_B12 = LCELL( _EQ023);
  _EQ023 =  _LC7_B12
         #  minhdis0 & !minhdis1
         #  hourldis0 &  minhdis0;

-- Node name is '~966~8' 
-- Equation name is '~966~8', location is LC2_B12, type is buried.
-- synthesized logic cell 
_LC2_B12 = LCELL( _EQ024);
  _EQ024 = !_LC4_B12 &  _LC8_B12
         # !hourhdis0 &  _LC8_B12
         # !_LC1_B6;

-- Node name is ':966' 
-- Equation name is '_LC1_B4', type is buried 
!_LC1_B4 = _LC1_B4~NOT;
_LC1_B4~NOT = LCELL( _EQ025);
  _EQ025 =  _LC2_B12 &  _LC3_B12
         #  hourhdis1
         # !_LC2_B1;

-- Node name is '~1100~1' 
-- Equation name is '~1100~1', location is LC2_B10, type is buried.
-- synthesized logic cell 
_LC2_B10 = LCELL( _EQ026);
  _EQ026 = !_LC3_B1 & !_LC6_B10 & !secldis0
         # !_LC3_B1 & !_LC8_B10;

-- Node name is '~1649~1' 
-- Equation name is '~1649~1', location is LC1_B1, type is buried.
-- synthesized logic cell 
_LC1_B1  = LCELL( _EQ027);
  _EQ027 = !_LC3_B10 &  _LC6_B1 & !secldis3
         # !_LC3_B10 & !_LC5_B1 &  _LC6_B1
         # !_LC5_B1 &  _LC6_B1 & !secldis3;

-- Node name is '~1649~2' 
-- Equation name is '~1649~2', location is LC4_B10, type is buried.
-- synthesized logic cell 
_LC4_B10 = LCELL( _EQ028);
  _EQ028 = !_LC3_B1 & !_LC6_B10 & !secldis0
         # !_LC3_B1 &  _LC6_B10 &  secldis0
         # !_LC8_B10;

-- Node name is ':1649' 
-- Equation name is '_LC8_B4', type is buried 
_LC8_B4  = LCELL( _EQ029);
  _EQ029 =  _LC1_B1 &  _LC4_B10;

-- Node name is ':2022' 
-- Equation name is '_LC2_B4', type is buried 
_LC2_B4  = LCELL( _EQ030);
  _EQ030 =  _LC1_B1 &  _LC1_B4 &  _LC2_B10
         #  _LC4_B4;

-- Node name is ':2028' 
-- Equation name is '_LC6_B4', type is buried 
_LC6_B4  = LCELL( _EQ031);
  _EQ031 =  _LC2_B4 & !_LC3_B4
         # !_LC2_B1 &  _LC2_B4
         #  _LC5_B4;

-- Node name is ':2029' 
-- Equation name is '_LC5_B4', type is buried 
_LC5_B4  = LCELL( _EQ032);
  _EQ032 =  _LC2_B1 &  _LC3_B4 &  _LC4_B4
         #  _LC2_B1 &  _LC3_B4 & !ONKEY;

-- Node name is ':2040' 
-- Equation name is '_LC4_B4', type is buried 
_LC4_B4  = LCELL( _EQ033);
  _EQ033 =  _LC6_B4 & !_LC7_B4 & !RESET
         #  _LC7_B4 &  _LC8_B4 & !RESET;



Project Information                                d:\autoring\timer_ring2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 24,927K