📄 timer_ring2.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\autoring\timer_ring2.rpt
timer_ring2
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
81 - - - 03 OUTPUT 0 1 0 0 ALARM
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\autoring\timer_ring2.rpt
timer_ring2
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 10 OR2 2 2 0 2 |LPM_ADD_SUB:400|addcore:adder|pcarry2
- 6 - B 10 OR2 1 1 0 2 |LPM_ADD_SUB:400|addcore:adder|:115
- 8 - B 10 OR2 2 2 0 2 |LPM_ADD_SUB:400|addcore:adder|:116
- 3 - B 01 OR2 1 2 0 2 |LPM_ADD_SUB:400|addcore:adder|:117
- 5 - B 01 OR2 2 0 0 2 |LPM_MULT:387|multcore:mult_core|:1378
- 5 - B 10 AND2 1 0 0 3 |LPM_MULT:387|multcore:mult_core|:1402
- 7 - B 10 AND2 1 0 0 2 |LPM_MULT:387|multcore:mult_core|:1405
- 1 - B 06 AND2 s 2 0 0 2 ~531~1
- 5 - B 06 AND2 s 2 1 0 1 ~531~2
- 1 - B 12 AND2 s 3 0 0 1 ~532~1
- 2 - B 06 OR2 s ! 1 3 0 1 ~532~2
- 7 - B 04 AND2 1 3 0 1 :532
- 4 - B 01 AND2 s 3 0 0 1 ~567~1
- 2 - B 01 AND2 s 3 1 0 4 ~567~2
- 6 - B 01 AND2 s 2 0 0 1 ~567~3
- 4 - B 06 AND2 s 2 0 0 2 ~567~4
- 1 - B 10 AND2 s 3 1 0 1 ~567~5
- 3 - B 04 AND2 s 3 1 0 2 ~567~6
- 4 - B 12 OR2 s ! 4 0 0 2 ~966~1
- 3 - B 06 AND2 s 3 0 0 2 ~966~2
- 3 - B 12 OR2 s 1 2 0 1 ~966~3
- 5 - B 12 OR2 s 3 0 0 1 ~966~4
- 6 - B 12 OR2 s ! 2 0 0 1 ~966~5
- 7 - B 12 OR2 s 2 2 0 1 ~966~6
- 8 - B 12 OR2 s 3 1 0 1 ~966~7
- 2 - B 12 OR2 s 1 3 0 1 ~966~8
- 1 - B 04 OR2 ! 1 3 0 1 :966
- 2 - B 10 OR2 s 1 3 0 1 ~1100~1
- 1 - B 01 OR2 s 1 3 0 2 ~1649~1
- 4 - B 10 OR2 s 1 3 0 1 ~1649~2
- 8 - B 04 AND2 0 2 0 1 :1649
- 2 - B 04 OR2 0 4 0 1 :2022
- 6 - B 04 OR2 0 4 0 1 :2028
- 5 - B 04 OR2 1 3 0 1 :2029
- 4 - B 04 OR2 1 3 1 2 :2040
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\autoring\timer_ring2.rpt
timer_ring2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 13/ 96( 13%) 17/ 48( 35%) 0/ 48( 0%) 9/16( 56%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\autoring\timer_ring2.rpt
timer_ring2
** EQUATIONS **
hourhdis0 : INPUT;
hourhdis1 : INPUT;
hourldis0 : INPUT;
hourldis1 : INPUT;
hourldis2 : INPUT;
hourldis3 : INPUT;
minhdis0 : INPUT;
minhdis1 : INPUT;
minhdis2 : INPUT;
minldis0 : INPUT;
minldis1 : INPUT;
minldis2 : INPUT;
minldis3 : INPUT;
ONKEY : INPUT;
RESET : INPUT;
sechdis0 : INPUT;
sechdis1 : INPUT;
sechdis2 : INPUT;
secldis0 : INPUT;
secldis1 : INPUT;
secldis2 : INPUT;
secldis3 : INPUT;
-- Node name is 'ALARM'
-- Equation name is 'ALARM', type is output
ALARM = _LC4_B4;
-- Node name is '|LPM_ADD_SUB:400|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_B10', type is buried
_LC3_B10 = LCELL( _EQ001);
_EQ001 = _LC7_B10 & secldis2
# _LC5_B10 & _LC7_B10 & secldis1
# _LC5_B10 & secldis1 & secldis2;
-- Node name is '|LPM_ADD_SUB:400|addcore:adder|:115' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC6_B10', type is buried
_LC6_B10 = LCELL( _EQ002);
_EQ002 = !_LC5_B10 & secldis1
# _LC5_B10 & !secldis1;
-- Node name is '|LPM_ADD_SUB:400|addcore:adder|:116' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC8_B10', type is buried
_LC8_B10 = LCELL( _EQ003);
_EQ003 = _LC5_B10 & !_LC7_B10 & secldis1 & !secldis2
# _LC7_B10 & !secldis1 & !secldis2
# !_LC5_B10 & _LC7_B10 & !secldis2
# _LC5_B10 & _LC7_B10 & secldis1 & secldis2
# !_LC7_B10 & !secldis1 & secldis2
# !_LC5_B10 & !_LC7_B10 & secldis2;
-- Node name is '|LPM_ADD_SUB:400|addcore:adder|:117' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC3_B1', type is buried
_LC3_B1 = LCELL( _EQ004);
_EQ004 = _LC3_B10 & _LC5_B1 & secldis3
# _LC3_B10 & !_LC5_B1 & !secldis3
# !_LC3_B10 & !_LC5_B1 & secldis3
# !_LC3_B10 & _LC5_B1 & !secldis3;
-- Node name is '|LPM_MULT:387|multcore:mult_core|:1378' from file "multcore.tdf" line 701, column 38
-- Equation name is '_LC5_B1', type is buried
_LC5_B1 = LCELL( _EQ005);
_EQ005 = sechdis0 & !sechdis2
# !sechdis0 & sechdis2;
-- Node name is '|LPM_MULT:387|multcore:mult_core|:1402' from file "multcore.tdf" line 702, column 38
-- Equation name is '_LC5_B10', type is buried
_LC5_B10 = LCELL( sechdis0);
-- Node name is '|LPM_MULT:387|multcore:mult_core|:1405' from file "multcore.tdf" line 702, column 38
-- Equation name is '_LC7_B10', type is buried
_LC7_B10 = LCELL( sechdis1);
-- Node name is '~531~1'
-- Equation name is '~531~1', location is LC1_B6, type is buried.
-- synthesized logic cell
_LC1_B6 = LCELL( _EQ006);
_EQ006 = !hourldis1 & !hourldis2;
-- Node name is '~531~2'
-- Equation name is '~531~2', location is LC5_B6, type is buried.
-- synthesized logic cell
_LC5_B6 = LCELL( _EQ007);
_EQ007 = _LC1_B6 & minhdis0 & minhdis1;
-- Node name is '~532~1'
-- Equation name is '~532~1', location is LC1_B12, type is buried.
-- synthesized logic cell
_LC1_B12 = LCELL( _EQ008);
_EQ008 = !hourldis0 & !hourldis3 & !minhdis2;
-- Node name is '~532~2'
-- Equation name is '~532~2', location is LC2_B6, type is buried.
-- synthesized logic cell
!_LC2_B6 = _LC2_B6~NOT;
_LC2_B6~NOT = LCELL( _EQ009);
_EQ009 = _LC3_B6 & _LC4_B6
# hourhdis0 & _LC5_B6;
-- Node name is ':532'
-- Equation name is '_LC7_B4', type is buried
_LC7_B4 = LCELL( _EQ010);
_EQ010 = !hourhdis1 & _LC1_B12 & _LC2_B1 & !_LC2_B6;
-- Node name is '~567~1'
-- Equation name is '~567~1', location is LC4_B1, type is buried.
-- synthesized logic cell
_LC4_B1 = LCELL( _EQ011);
_EQ011 = !minldis0 & !sechdis1 & !sechdis2;
-- Node name is '~567~2'
-- Equation name is '~567~2', location is LC2_B1, type is buried.
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