adringup.rpt

关于自动打铃器的程序设计。应该还是不错的哦！~

  _EQ002 =  _LC5_A12 & !secldis1
         # !_LC5_A12 &  secldis1;

-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:116' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC6_A12', type is buried 
_LC6_A12 = LCELL( _EQ003);
  _EQ003 = !_LC5_A12 &  _LC7_A12 & !secldis2
         #  _LC7_A12 & !secldis1 & !secldis2
         #  _LC5_A12 & !_LC7_A12 &  secldis1 & !secldis2
         #  _LC5_A12 &  _LC7_A12 &  secldis1 &  secldis2
         # !_LC5_A12 & !_LC7_A12 &  secldis2
         # !_LC7_A12 & !secldis1 &  secldis2;

-- Node name is '|LPM_MULT:171|multcore:mult_core|:1378' from file "multcore.tdf" line 701, column 38
-- Equation name is '_LC2_A10', type is buried 
!_LC2_A10 = _LC2_A10~NOT;
_LC2_A10~NOT = LCELL( _EQ004);
  _EQ004 =  sechdis0 &  sechdis2
         # !sechdis0 & !sechdis2;

-- Node name is '|LPM_MULT:171|multcore:mult_core|:1402' from file "multcore.tdf" line 702, column 38
-- Equation name is '_LC5_A12', type is buried 
_LC5_A12 = LCELL( sechdis0);

-- Node name is '|LPM_MULT:171|multcore:mult_core|:1405' from file "multcore.tdf" line 702, column 38
-- Equation name is '_LC7_A12', type is buried 
_LC7_A12 = LCELL( sechdis1);

-- Node name is '~312~1' 
-- Equation name is '~312~1', location is LC1_A12, type is buried.
-- synthesized logic cell 
_LC1_A12 = LCELL( _EQ005);
  _EQ005 =  _LC1_A10 & !sechdis0 & !secldis1 & !secldis2;

-- Node name is '~419~1' 
-- Equation name is '~419~1', location is LC3_A10, type is buried.
-- synthesized logic cell 
_LC3_A10 = LCELL( _EQ006);
  _EQ006 = !minldis0 & !minldis1 & !minldis2;

-- Node name is '~419~2' 
-- Equation name is '~419~2', location is LC4_A10, type is buried.
-- synthesized logic cell 
_LC4_A10 = LCELL( _EQ007);
  _EQ007 =  _LC3_A10 & !minhdis0 & !minhdis1 & !minldis3;

-- Node name is '~419~3' 
-- Equation name is '~419~3', location is LC1_A10, type is buried.
-- synthesized logic cell 
_LC1_A10 = LCELL( _EQ008);
  _EQ008 =  _LC4_A10 & !minhdis2 & !sechdis1 & !sechdis2;

-- Node name is '~419~4' 
-- Equation name is '~419~4', location is LC8_A12, type is buried.
-- synthesized logic cell 
!_LC8_A12 = _LC8_A12~NOT;
_LC8_A12~NOT = LCELL( _EQ009);
  _EQ009 = !hourldis2
         # !hourldis1
         #  hourldis0
         # !_LC1_A10;

-- Node name is ':419' 
-- Equation name is '_LC2_A12', type is buried 
!_LC2_A12 = _LC2_A12~NOT;
_LC2_A12~NOT = LCELL( _EQ010);
  _EQ010 = !_LC8_A12
         #  hourhdis1
         #  hourhdis0
         #  hourldis3;

-- Node name is '~608~1' 
-- Equation name is '~608~1', location is LC4_A1, type is buried.
-- synthesized logic cell 
_LC4_A1  = LCELL( _EQ011);
  _EQ011 = !_LC2_A10 & !_LC4_A12 & !secldis3;

-- Node name is ':608' 
-- Equation name is '_LC6_A1', type is buried 
_LC6_A1  = LCELL( _EQ012);
  _EQ012 =  _LC4_A1 & !_LC6_A12
         # !_LC3_A12 &  _LC4_A1 & !secldis0;

-- Node name is '~966~1' 
-- Equation name is '~966~1', location is LC2_A1, type is buried.
-- synthesized logic cell 
_LC2_A1  = LCELL( _EQ013);
  _EQ013 =  _LC5_A12 &  secldis0 & !secldis1
         # !_LC5_A12 &  secldis0 &  secldis1
         #  _LC5_A12 & !secldis0 &  secldis1
         # !_LC5_A12 & !secldis0 & !secldis1
         # !_LC6_A12;

-- Node name is ':1093' 
-- Equation name is '_LC3_A1', type is buried 
_LC3_A1  = LCELL( _EQ014);
  _EQ014 = !_LC2_A10 & !_LC4_A12 & !secldis3
         # !_LC2_A10 & !_LC6_A12 & !secldis3
         # !_LC2_A10 & !_LC4_A12 & !_LC6_A12
         # !_LC4_A12 & !_LC6_A12 & !secldis3;

-- Node name is ':1157' 
-- Equation name is '_LC5_A1', type is buried 
_LC5_A1  = LCELL( _EQ015);
  _EQ015 =  _LC1_A1 &  _LC2_A1
         #  _LC2_A1 &  _LC3_A1
         #  _LC1_A1 & !_LC4_A1
         #  _LC3_A1 & !_LC4_A1;

-- Node name is ':1168' 
-- Equation name is '_LC7_A1', type is buried 
_LC7_A1  = LCELL( _EQ016);
  _EQ016 =  _LC2_A12 &  _LC5_A1
         #  _LC2_A12 &  _LC6_A1
         #  _LC1_A1 & !_LC2_A12;

-- Node name is ':1183' 
-- Equation name is '_LC8_A1', type is buried 
_LC8_A1  = LCELL( _EQ017);
  _EQ017 =  _LC1_A1
         #  _LC1_A12 & !secldis0 & !secldis3;

-- Node name is ':1195' 
-- Equation name is '_LC1_A1', type is buried 
_LC1_A1  = LCELL( _EQ018);
  _EQ018 = !bsset &  _LC7_A1 & !reset
         #  bsset &  _LC8_A1 & !reset;



Project Informatione:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\adringup.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 17,460K