📄 adringup.rpt
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Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 7/ 576 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 0 0 0 0 0 0 0 0 4 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 20/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 8 0 0 0 0 0 0 0 0 4 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 20/0
Device-Specific Information:e:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\adringup.rpt
adringup
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
141 - - A -- INPUT ^ 0 0 0 1 bsset
11 - - A -- INPUT ^ 0 0 0 1 hourhdis0
90 - - - 08 INPUT ^ 0 0 0 1 hourhdis1
144 - - A -- INPUT ^ 0 0 0 1 hourldis0
88 - - - 10 INPUT ^ 0 0 0 1 hourldis1
173 - - - 09 INPUT ^ 0 0 0 1 hourldis2
18 - - A -- INPUT ^ 0 0 0 1 hourldis3
10 - - A -- INPUT ^ 0 0 0 1 minhdis0
148 - - A -- INPUT ^ 0 0 0 1 minhdis1
143 - - A -- INPUT ^ 0 0 0 1 minhdis2
95 - - - 06 INPUT ^ 0 0 0 1 minldis0
12 - - A -- INPUT ^ 0 0 0 1 minldis1
104 - - - 01 INPUT ^ 0 0 0 1 minldis2
19 - - A -- INPUT ^ 0 0 0 1 minldis3
16 - - A -- INPUT ^ 0 0 0 1 reset
78 - - - -- INPUT ^ 0 0 0 3 sechdis0
182 - - - -- INPUT ^ 0 0 0 2 sechdis1
183 - - - -- INPUT ^ 0 0 0 2 sechdis2
184 - - - -- INPUT ^ 0 0 0 3 secldis0
80 - - - -- INPUT ^ 0 0 0 5 secldis1
79 - - - -- INPUT ^ 0 0 0 3 secldis2
142 - - A -- INPUT ^ 0 0 0 3 secldis3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\adringup.rpt
adringup
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
150 - - A -- OUTPUT 0 1 0 0 alarm
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\adringup.rpt
adringup
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 12 OR2 ! 2 2 0 2 |LPM_ADD_SUB:184|addcore:adder|pcarry2
- 3 - A 12 OR2 1 1 0 1 |LPM_ADD_SUB:184|addcore:adder|:115
- 6 - A 12 OR2 2 2 0 3 |LPM_ADD_SUB:184|addcore:adder|:116
- 2 - A 10 OR2 ! 2 0 0 2 |LPM_MULT:171|multcore:mult_core|:1378
- 5 - A 12 AND2 1 0 0 4 |LPM_MULT:171|multcore:mult_core|:1402
- 7 - A 12 AND2 1 0 0 2 |LPM_MULT:171|multcore:mult_core|:1405
- 1 - A 12 AND2 s 3 1 0 1 ~312~1
- 3 - A 10 AND2 s 3 0 0 1 ~419~1
- 4 - A 10 AND2 s 3 1 0 1 ~419~2
- 1 - A 10 AND2 s 3 1 0 2 ~419~3
- 8 - A 12 OR2 s ! 3 1 0 1 ~419~4
- 2 - A 12 OR2 ! 3 1 0 1 :419
- 4 - A 01 AND2 s 1 2 0 2 ~608~1
- 6 - A 01 OR2 1 3 0 1 :608
- 2 - A 01 OR2 s 2 2 0 1 ~966~1
- 3 - A 01 OR2 1 3 0 1 :1093
- 5 - A 01 OR2 0 4 0 1 :1157
- 7 - A 01 OR2 0 4 0 1 :1168
- 8 - A 01 OR2 2 2 0 1 :1183
- 1 - A 01 OR2 2 2 1 3 :1195
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information:e:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\adringup.rpt
adringup
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 13/ 96( 13%) 12/ 48( 25%) 0/ 48( 0%) 11/16( 68%) 1/16( 6%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\adringup.rpt
adringup
** EQUATIONS **
bsset : INPUT;
hourhdis0 : INPUT;
hourhdis1 : INPUT;
hourldis0 : INPUT;
hourldis1 : INPUT;
hourldis2 : INPUT;
hourldis3 : INPUT;
minhdis0 : INPUT;
minhdis1 : INPUT;
minhdis2 : INPUT;
minldis0 : INPUT;
minldis1 : INPUT;
minldis2 : INPUT;
minldis3 : INPUT;
reset : INPUT;
sechdis0 : INPUT;
sechdis1 : INPUT;
sechdis2 : INPUT;
secldis0 : INPUT;
secldis1 : INPUT;
secldis2 : INPUT;
secldis3 : INPUT;
-- Node name is 'alarm'
-- Equation name is 'alarm', type is output
alarm = _LC1_A1;
-- Node name is '|LPM_ADD_SUB:184|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_A12', type is buried
!_LC4_A12 = _LC4_A12~NOT;
_LC4_A12~NOT = LCELL( _EQ001);
_EQ001 = !_LC7_A12 & !secldis2
# !_LC5_A12 & !_LC7_A12
# !_LC5_A12 & !secldis2
# !_LC7_A12 & !secldis1
# !secldis1 & !secldis2;
-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:115' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC3_A12', type is buried
_LC3_A12 = LCELL( _EQ002);
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