📄 autoring02.rpt
字号:
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
m R R R R h G R h R R R s V R R R m m V R R R G V e c k G G R V R R R R R s V s s s s R R V R R m m R R
h E E E E l N E h E E E h C E E E h h C E E E N C n l e N N E C E E E E E h C h l l l E E C E E l l E E
4 S S S S 0 D S 7 S S S 7 C S S S 3 5 C S S S D C t k y D D S C S S S S S 5 C 3 5 6 1 S S C S S 5 6 S S
E E E E E E E E I E E E I E E E I e u E I E E E E E I E E I E E E E
R R R R R R R R O R R R N R R R N r p R O R R R R R N R R O R R R R
V V V V V V V V V V V T V V V T V V V V V V T V V V V V V
E E E E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: f:\autoring\autoring02.rpt
autoring02
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A16 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
C3 8/ 8(100%) 7/ 8( 87%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
C4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 0/22( 0%)
C5 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 8/22( 36%)
C8 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 2/2 2/2 6/22( 27%)
C9 8/ 8(100%) 5/ 8( 62%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
C10 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 3/22( 13%)
C11 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 2/2 1/2 5/22( 22%)
C12 4/ 8( 50%) 3/ 8( 37%) 1/ 8( 12%) 1/2 0/2 3/22( 13%)
C14 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 0/22( 0%)
C16 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 7/22( 31%)
C21 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 1/22( 4%)
C22 8/ 8(100%) 5/ 8( 62%) 2/ 8( 25%) 2/2 1/2 6/22( 27%)
C23 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 8/22( 36%)
C24 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 2/2 2/2 8/22( 36%)
C25 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 2/2 9/22( 40%)
C32 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 1/2 0/2 4/22( 18%)
C35 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 8/22( 36%)
C36 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
D27 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
E23 6/ 8( 75%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 2/22( 9%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 49/141 ( 34%)
Total logic cells used: 125/1728 ( 7%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.13/4 ( 78%)
Total fan-in: 392/6912 ( 5%)
Total input pins required: 6
Total input I/O cell registers required: 0
Total output pins required: 49
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 125
Total flipflops required: 83
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 22/1728 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 8 1 8 0 0 8 8 8 8 4 0 1 0 7 0 0 0 0 0 7 8 8 8 8 0 0 0 0 0 0 8 0 0 8 1 117/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 6/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 8 1 8 0 0 8 8 8 8 4 0 1 0 8 0 0 0 0 0 7 8 14 8 8 0 1 0 0 0 0 8 0 0 8 1 125/0
Device-Specific Information: f:\autoring\autoring02.rpt
autoring02
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
182 - - - -- INPUT G ^ 0 0 0 0 begend
79 - - - -- INPUT G ^ 0 0 0 0 clk
78 - - - -- INPUT G ^ 0 0 0 0 enter
80 - - - -- INPUT G ^ 0 0 0 0 keyup
184 - - - -- INPUT G ^ 0 0 0 1 reset
183 - - - -- INPUT G ^ 0 0 0 0 sclk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\autoring\autoring02.rpt
autoring02
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
25 - - D -- OUTPUT 0 1 0 0 alarm
41 - - E -- OUTPUT 0 1 0 0 hh0
149 - - A -- OUTPUT 0 1 0 0 hh1
39 - - E -- OUTPUT 0 1 0 0 hh2
40 - - E -- OUTPUT 0 1 0 0 hh3
36 - - E -- OUTPUT 0 1 0 0 hh4
37 - - E -- OUTPUT 0 1 0 0 hh5
38 - - E -- OUTPUT 0 1 0 0 hh6
61 - - - 29 OUTPUT 0 0 0 0 hh7
58 - - - 31 OUTPUT 0 1 0 0 hl0
24 - - C -- OUTPUT 0 1 0 0 hl1
132 - - C -- OUTPUT 0 1 0 0 hl2
203 - - - 32 OUTPUT 0 1 0 0 hl3
19 - - C -- OUTPUT 0 1 0 0 hl4
202 - - - 31 OUTPUT 0 1 0 0 hl5
18 - - C -- OUTPUT 0 1 0 0 hl6
187 - - - 20 OUTPUT 0 0 0 0 hl7
135 - - C -- OUTPUT 0 1 0 0 mh0
15 - - B -- OUTPUT 0 1 0 0 mh1
189 - - - 21 OUTPUT 0 1 0 0 mh2
70 - - - 22 OUTPUT 0 1 0 0 mh3
53 - - - 36 OUTPUT 0 1 0 0 mh4
71 - - - 21 OUTPUT 0 1 0 0 mh5
190 - - - 22 OUTPUT 0 1 0 0 mh6
111 - - F -- OUTPUT 0 0 0 0 mh7
47 - - F -- OUTPUT 0 1 0 0 ml0
143 - - B -- OUTPUT 0 1 0 0 ml1
160 - - - 04 OUTPUT 0 1 0 0 ml2
161 - - - 04 OUTPUT 0 1 0 0 ml3
159 - - - 03 OUTPUT 0 1 0 0 ml4
101 - - - 04 OUTPUT 0 1 0 0 ml5
102 - - - 03 OUTPUT 0 1 0 0 ml6
204 - - - 33 OUTPUT 0 0 0 0 ml7
170 - - - 11 OUTPUT 0 1 0 0 sh0
172 - - - 12 OUTPUT 0 1 0 0 sh1
45 - - F -- OUTPUT 0 1 0 0 sh2
92 - - - 11 OUTPUT 0 1 0 0 sh3
131 - - C -- OUTPUT 0 1 0 0 sh4
90 - - - 12 OUTPUT 0 1 0 0 sh5
115 - - F -- OUTPUT 0 1 0 0 sh6
65 - - - 26 OUTPUT 0 0 0 0 sh7
168 - - - 09 OUTPUT 0 1 0 0 sl0
95 - - - 09 OUTPUT 0 1 0 0 sl1
169 - - - 10 OUTPUT 0 1 0 0 sl2
17 - - C -- OUTPUT 0 1 0 0 sl3
133 - - C -- OUTPUT 0 1 0 0 sl4
93 - - - 10 OUTPUT 0 1 0 0 sl5
94 - - - 09 OUTPUT 0 1 0 0 sl6
147 - - A -- OUTPUT 0 0 0 0 sl7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\autoring\autoring02.rpt
autoring02
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 35 OR2 ! 0 3 0 1 |CLOCKRUN:1|LPM_ADD_SUB:365|addcore:adder|:63
- 7 - C 05 AND2 0 2 0 1 |CLOCKRUN:1|LPM_ADD_SUB:563|addcore:adder|:59
- 3 - C 05 AND2 0 3 0 1 |CLOCKRUN:1|LPM_ADD_SUB:563|addcore:adder|:63
- 4 - C 16 AND2 0 2 0 1 |CLOCKRUN:1|LPM_ADD_SUB:838|addcore:adder|:59
- 1 - C 16 AND2 0 3 0 1 |CLOCKRUN:1|LPM_ADD_SUB:838|addcore:adder|:63
- 2 - C 16 DFFE + 0 4 0 8 |CLOCKRUN:1|seclow3 (|CLOCKRUN:1|:43)
- 6 - C 16 DFFE + 0 4 0 9 |CLOCKRUN:1|seclow2 (|CLOCKRUN:1|:44)
- 8 - C 16 DFFE + 0 4 0 10 |CLOCKRUN:1|seclow1 (|CLOCKRUN:1|:45)
- 3 - C 16 DFFE + 0 2 0 11 |CLOCKRUN:1|seclow0 (|CLOCKRUN:1|:46)
- 2 - C 11 DFFE + 0 3 0 9 |CLOCKRUN:1|sechigh2 (|CLOCKRUN:1|:47)
- 4 - C 11 DFFE + 0 3 0 9 |CLOCKRUN:1|sechigh1 (|CLOCKRUN:1|:48)
- 6 - C 08 DFFE + 0 3 0 9 |CLOCKRUN:1|sechigh0 (|CLOCKRUN:1|:49)
- 7 - C 16 DFFE + 0 4 0 9 |CLOCKRUN:1|minlow3 (|CLOCKRUN:1|:50)
- 4 - C 05 DFFE + 0 4 0 10 |CLOCKRUN:1|minlow2 (|CLOCKRUN:1|:51)
- 5 - C 05 DFFE + 0 4 0 11 |CLOCKRUN:1|minlow1 (|CLOCKRUN:1|:52)
- 2 - C 05 DFFE + 0 4 0 11 |CLOCKRUN:1|minlow0 (|CLOCKRUN:1|:53)
- 1 - C 22 DFFE + 0 4 0 11 |CLOCKRUN:1|minhigh2 (|CLOCKRUN:1|:54)
- 6 - C 23 DFFE + 0 5 0 10 |CLOCKRUN:1|minhigh1 (|CLOCKRUN:1|:55)
- 8 - C 08 DFFE + 0 4 0 10 |CLOCKRUN:1|minhigh0 (|CLOCKRUN:1|:56)
- 2 - C 35 DFFE + 0 5 0 11 |CLOCKRUN:1|hourlow3 (|CLOCKRUN:1|:57)
- 1 - C 25 DFFE + 0 4 0 11 |CLOCKRUN:1|hourlow2 (|CLOCKRUN:1|:58)
- 4 - C 35 DFFE + 0 5 0 21 |CLOCKRUN:1|hourlow1 (|CLOCKRUN:1|:59)
- 4 - C 25 DFFE + 0 3 0 19 |CLOCKRUN:1|hourlow0 (|CLOCKRUN:1|:60)
- 7 - C 24 AND2 s 0 4 0 1 |CLOCKRUN:1|hourhigh1~1 (|CLOCKRUN:1|~61~1)
- 8 - C 24 DFFE + 0 4 0 2 |CLOCKRUN:1|hourhigh1 (|CLOCKRUN:1|:61)
- 4 - C 24 DFFE + 0 4 0 3 |CLOCKRUN:1|hourhigh0 (|CLOCKRUN:1|:62)
- 2 - C 08 AND2 s 0 2 0 3 |CLOCKRUN:1|~219~1
- 6 - C 35 AND2 s 0 2 0 2 |CLOCKRUN:1|~219~2
- 7 - C 25 AND2 s 0 4 0 1 |CLOCKRUN:1|~219~3
- 1 - C 23 AND2 s 0 2 0 2 |CLOCKRUN:1|~219~4
- 4 - C 22 AND2 s 0 4 0 1 |CLOCKRUN:1|~219~5
- 1 - C 09 AND2 0 4 0 11 |CLOCKRUN:1|:219
- 1 - C 11 AND2 0 3 0 6 |CLOCKRUN:1|:235
- 8 - C 03 AND2 0 4 0 6 |CLOCKRUN:1|:251
- 3 - C 24 AND2 0 4 0 4 |CLOCKRUN:1|:292
- 7 - C 23 AND2 s 0 3 0 5 |CLOCKRUN:1|~501~1
- 5 - C 24 OR2 s 0 4 0 2 |CLOCKRUN:1|~513~1
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -