div.vhd.bak

来自「pwm控制模块 使用过很多次」· BAK 代码 · 共 37 行

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity div is
port ( clk10k:in std_logic;
       ctr:in integer range 16 to 64;
       pwm:out std_logic     
      );
end div;



architecture ddiv of div is
signal cnt: integer range 0 to 79;
begin
process(clk10k)
begin
if clk10k'event and clk10k='1' then
   if cnt=79 then cnt<=0;
   else cnt<=cnt+1;
   end if;
end if;
end process;

process(clk10k)
begin
if clk10k'event and clk10k='1' then
   if cnt<ctr then
         pwm<='1';
   else  rpwm<='0';
   end if;
end if;
end process;

end ddiv;