tt.vhd.bak

pwm控制模块 使用过很多次

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity tt is
port ( clk10k:in std_logic;
       color:in integer range 0 to 2;
       key2:in std_logic;
       key3:in std_logic;      
       gpwm0_ctr:out integer range 16 to 64;
       gpwm1_ctr:out integer range 16 to 64;
       gpwm2_ctr:out integer range 16 to 64;
       gpwm3_ctr:out integer range 16 to 64;
       gpwm4_ctr:out integer range 16 to 64;
       gpwm5_ctr:out integer range 16 to 64
       );
end tt;

architecture rsle of tt is
signal branch:integer range 0 to 5;
signal ctr:integer range 16 to 64;
signal ctr0:integer range 16 to 64;
signal ctr1:integer range 16 to 64;
signal ctr2:integer range 16 to 64;
signal ctr3:integer range 16 to 64;
signal ctr4:integer range 16 to 64;
signal ctr5:integer range 16 to 64;
begin

process(key2,color)
begin
if color=1 then
if key2'event and key2='1' then
   if branch=5 then
      branch<=0;
   else branch<=branch+1;
   end if;
end if;
else null;
end if;
end process;


process(key3,color)
begin
if color=1 then
if key3'event and key3='1' then
   if branch=0 then
      if ctr0=64 then
         ctr0<=16;
      else ctr0<=ctr0+16;
      end if;
   elsif branch=1 then
      if ctr1=64 then
         ctr1<=16;
      else ctr1<=ctr1+16;
      end if;
   elsif branch=2 then
      if ctr2=64 then
         ctr<=16;
      else ctr2<=ctr2+16;
      end if;
   elsif branch=3 then
      if ctr3=64 then
         ctr3<=16;
      else ctr3<=ctr3+16;
      end if;
   elsif branch=4 then
      if ctr4=64 then
         ctr4<=16;
      else ctr4<=ctr4+16;
      end if;
   elsif branch=5 then
      if ctr5=64 then
         ctr5<=16;
      else ctr5<=ctr5+16;
      end if;
    end if;
end if;
else null;
end if;
end process;

process(clk10k,color)
begin
if color=1 then
if clk10k'event and clk10k='1' then
case branch is
            when 0 =>ctr0<=ctr;
            when 1 =>ctr1<=ctr;
            when 2 =>ctr2<=ctr;
            when 3 =>ctr3<=ctr;
            when 4 =>ctr4<=ctr;
            when 5 =>ctr5<=ctr;

end case;
end if;
end if;
end process;

gpwm0_ctr<=ctr0;
gpwm1_ctr<=ctr1;
gpwm2_ctr<=ctr2;
gpwm3_ctr<=ctr3;
gpwm4_ctr<=ctr4;
gpwm5_ctr<=ctr5;



end rsle;