test.vhd.bak

pwm控制模块 使用过很多次

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity test is
port ( clk10k:in std_logic;
       color:in integer range 0 to 2;
       key2:in std_logic;
       key3:in std_logic;      
       bpwm0_ctr:out integer range 16 to 64;
       bpwm1_ctr:out integer range 16 to 64;
       bpwm2_ctr:out integer range 16 to 64;
       bpwm3_ctr:out integer range 16 to 64;
       bpwm4_ctr:out integer range 16 to 64;
       bpwm5_ctr:out integer range 16 to 64
       );
end test;

architecture rsle of test is
signal branch:integer range 0 to 5;
signal ctr:integer range 16 to 64;
signal ctr0:integer range 16 to 64;
signal ctr1:integer range 16 to 64;
signal ctr2:integer range 16 to 64;
signal ctr3:integer range 16 to 64;
signal ctr4:integer range 16 to 64;
signal ctr5:integer range 16 to 64;
begin

process(key2,color)
begin
if color=2 then
if key2'event and key2='1' then
   if branch=15 then
      branch<=0;
   else branch<=branch+1;
   end if;
end if;
end if;
end process;


process(key3,color)
begin
if color=2 then
if key3'event and key3='1' then
   if ctr=64 then
      ctr<=16;
   else ctr<=ctr+16;
   end if;
end if;
end if;
end process;

process(color)
begin
if color=2 then
case branch is
            when 0 =>ctr0<=ctr;
            when 1 =>ctr1<=ctr;
            when 2 =>ctr2<=ctr;
            when 3 =>ctr3<=ctr;
            when 4 =>ctr4<=ctr;
            when 5 =>ctr5<=ctr;
end case;
end if;
end process;

bpwm0_ctr<=ctr0;
bpwm1_ctr<=ctr1;
bpwm2_ctr<=ctr2;
bpwm3_ctr<=ctr3;
bpwm4_ctr<=ctr4;
bpwm5_ctr<=ctr5;

end rsle;