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📄 prev_cmp_ctr.map.qmsg

📁 pwm控制模块 使用过很多次
💻 QMSG
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{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "gslect:inst59\|ctr0\[0\] data_in GND " "Warning (14130): Reduced register \"gslect:inst59\|ctr0\[0\]\" with stuck data_in port to stuck value GND" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "gslect:inst59\|ctr1\[1\] data_in GND " "Warning (14130): Reduced register \"gslect:inst59\|ctr1\[1\]\" with stuck data_in port to stuck value GND" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "gslect:inst59\|ctr1\[0\] data_in GND " "Warning (14130): Reduced register \"gslect:inst59\|ctr1\[0\]\" with stuck data_in port to stuck value GND" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "gslect:inst59\|ctr2\[1\] data_in GND " "Warning (14130): Reduced register \"gslect:inst59\|ctr2\[1\]\" with stuck data_in port to stuck value GND" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "gslect:inst59\|ctr2\[0\] data_in GND " "Warning (14130): Reduced register \"gslect:inst59\|ctr2\[0\]\" with stuck data_in port to stuck value GND" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "gslect:inst59\|ctr3\[1\] data_in GND " "Warning (14130): Reduced register \"gslect:inst59\|ctr3\[1\]\" with stuck data_in port to stuck value GND" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "gslect:inst59\|ctr3\[0\] data_in GND " "Warning (14130): Reduced register \"gslect:inst59\|ctr3\[0\]\" with stuck data_in port to stuck value GND" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rrselect:inst58\|ctr0\[1\] data_in GND " "Warning (14130): Reduced register \"rrselect:inst58\|ctr0\[1\]\" with stuck data_in port to stuck value GND" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rrselect:inst58\|ctr0\[0\] data_in GND " "Warning (14130): Reduced register \"rrselect:inst58\|ctr0\[0\]\" with stuck data_in port to stuck value GND" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rrselect:inst58\|ctr1\[1\] data_in GND " "Warning (14130): Reduced register \"rrselect:inst58\|ctr1\[1\]\" with stuck data_in port to stuck value GND" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rrselect:inst58\|ctr1\[0\] data_in GND " "Warning (14130): Reduced register \"rrselect:inst58\|ctr1\[0\]\" with stuck data_in port to stuck value GND" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rrselect:inst58\|ctr2\[1\] data_in GND " "Warning (14130): Reduced register \"rrselect:inst58\|ctr2\[1\]\" with stuck data_in port to stuck value GND" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rrselect:inst58\|ctr2\[0\] data_in GND " "Warning (14130): Reduced register \"rrselect:inst58\|ctr2\[0\]\" with stuck data_in port to stuck value GND" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rrselect:inst58\|ctr3\[1\] data_in GND " "Warning (14130): Reduced register \"rrselect:inst58\|ctr3\[1\]\" with stuck data_in port to stuck value GND" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rrselect:inst58\|ctr3\[0\] data_in GND " "Warning (14130): Reduced register \"rrselect:inst58\|ctr3\[0\]\" with stuck data_in port to stuck value GND" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "bslect:inst60\|ctr15\[1\] bslect:inst60\|ctr15\[0\] " "Info: Duplicate register \"bslect:inst60\|ctr15\[1\]\" merged to single register \"bslect:inst60\|ctr15\[0\]\"" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "bslect:inst60\|ctr4\[0\] bslect:inst60\|ctr4\[1\] " "Info: Duplicate register \"bslect:inst60\|ctr4\[0\]\" merged to single register \"bslect:inst60\|ctr4\[1\]\"" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "bslect:inst60\|ctr5\[0\] bslect:inst60\|ctr5\[1\] " "Info: Duplicate register \"bslect:inst60\|ctr5\[0\]\" merged to single register \"bslect:inst60\|ctr5\[1\]\"" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "bslect:inst60\|ctr6\[0\] bslect:inst60\|ctr6\[1\] " "Info: Duplicate register \"bslect:inst60\|ctr6\[0\]\" merged to single register \"bslect:inst60\|ctr6\[1\]\"" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "bslect:inst60\|ctr7\[0\] bslect:inst60\|ctr7\[1\] " "Info: Duplicate register \"bslect:inst60\|ctr7\[0\]\" merged to single register \"bslect:inst60\|ctr7\[1\]\"" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "bslect:inst60\|ctr8\[0\] bslect:inst60\|ctr8\[1\] " "Info: Duplicate register \"bslect:inst60\|ctr8\[0\]\" merged to single register \"bslect:inst60\|ctr8\[1\]\"" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "bslect:inst60\|ctr9\[0\] bslect:inst60\|ctr9\[1\] " "Info: Duplicate register \"bslect:inst60\|ctr9\[0\]\" merged to single register \"bslect:inst60\|ctr9\[1\]\"" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "bslect:inst60\|ctr10\[0\] bslect:inst60\|ctr10\[1\] " "Info: Duplicate register \"bslect:inst60\|ctr10\[0\]\" merged to single register \"bslect:inst60\|ctr10\[1\]\"" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "bslect:inst60\|ctr11\[0\] bslect:inst60\|ctr11\[1\] " "Info: Duplicate register \"bslect:inst60\|ctr11\[0\]\" merged to single register \"bslect:inst60\|ctr11\[1\]\"" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "bslect:inst60\|ctr12\[0\] bslect:inst60\|ctr12\[1\] " "Info: Duplicate register \"bslect:inst60\|ctr12\[0\]\" merged to single register \"bslect:inst60\|ctr12\[1\]\"" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "bslect:inst60\|ctr13\[0\] bslect:inst60\|ctr13\[1\] " "Info: Duplicate register \"bslect:inst60\|ctr13\[0\]\" merged to single register \"bslect:inst60\|ctr13\[1\]\"" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "bslect:inst60\|ctr14\[0\] bslect:inst60\|ctr14\[1\] " "Info: Duplicate register \"bslect:inst60\|ctr14\[0\]\" merged to single register \"bslect:inst60\|ctr14\[1\]\"" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gslect:inst59\|ctr15\[1\] gslect:inst59\|ctr15\[0\] " "Info: Duplicate register \"gslect:inst59\|ctr15\[1\]\" merged to single register \"gslect:inst59\|ctr15\[0\]\"" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gslect:inst59\|ctr4\[0\] gslect:inst59\|ctr4\[1\] " "Info: Duplicate register \"gslect:inst59\|ctr4\[0\]\" merged to single register \"gslect:inst59\|ctr4\[1\]\"" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gslect:inst59\|ctr5\[0\] gslect:inst59\|ctr5\[1\] " "Info: Duplicate register \"gslect:inst59\|ctr5\[0\]\" merged to single register \"gslect:inst59\|ctr5\[1\]\"" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gslect:inst59\|ctr6\[0\] gslect:inst59\|ctr6\[1\] " "Info: Duplicate register \"gslect:inst59\|ctr6\[0\]\" merged to single register \"gslect:inst59\|ctr6\[1\]\"" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gslect:inst59\|ctr7\[0\] gslect:inst59\|ctr7\[1\] " "Info: Duplicate register \"gslect:inst59\|ctr7\[0\]\" merged to single register \"gslect:inst59\|ctr7\[1\]\"" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gslect:inst59\|ctr8\[0\] gslect:inst59\|ctr8\[1\] " "Info: Duplicate register \"gslect:inst59\|ctr8\[0\]\" merged to single register \"gslect:inst59\|ctr8\[1\]\"" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gslect:inst59\|ctr9\[0\] gslect:inst59\|ctr9\[1\] " "Info: Duplicate register \"gslect:inst59\|ctr9\[0\]\" merged to single register \"gslect:inst59\|ctr9\[1\]\"" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gslect:inst59\|ctr10\[0\] gslect:inst59\|ctr10\[1\] " "Info: Duplicate register \"gslect:inst59\|ctr10\[0\]\" merged to single register \"gslect:inst59\|ctr10\[1\]\"" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gslect:inst59\|ctr11\[0\] gslect:inst59\|ctr11\[1\] " "Info: Duplicate register \"gslect:inst59\|ctr11\[0\]\" merged to single register \"gslect:inst59\|ctr11\[1\]\"" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gslect:inst59\|ctr12\[0\] gslect:inst59\|ctr12\[1\] " "Info: Duplicate register \"gslect:inst59\|ctr12\[0\]\" merged to single register \"gslect:inst59\|ctr12\[1\]\"" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gslect:inst59\|ctr13\[0\] gslect:inst59\|ctr13\[1\] " "Info: Duplicate register \"gslect:inst59\|ctr13\[0\]\" merged to single register \"gslect:inst59\|ctr13\[1\]\"" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "gslect:inst59\|ctr14\[0\] gslect:inst59\|ctr14\[1\] " "Info: Duplicate register \"gslect:inst59\|ctr14\[0\]\" merged to single register \"gslect:inst59\|ctr14\[1\]\"" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rrselect:inst58\|ctr15\[1\] rrselect:inst58\|ctr15\[0\] " "Info: Duplicate register \"rrselect:inst58\|ctr15\[1\]\" merged to single register \"rrselect:inst58\|ctr15\[0\]\"" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rrselect:inst58\|ctr4\[0\] rrselect:inst58\|ctr4\[1\] " "Info: Duplicate register \"rrselect:inst58\|ctr4\[0\]\" merged to single register \"rrselect:inst58\|ctr4\[1\]\"" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rrselect:inst58\|ctr5\[0\] rrselect:inst58\|ctr5\[1\] " "Info: Duplicate register \"rrselect:inst58\|ctr5\[0\]\" merged to single register \"rrselect:inst58\|ctr5\[1\]\"" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rrselect:inst58\|ctr6\[0\] rrselect:inst58\|ctr6\[1\] " "Info: Duplicate register \"rrselect:inst58\|ctr6\[0\]\" merged to single register \"rrselect:inst58\|ctr6\[1\]\"" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rrselect:inst58\|ctr7\[0\] rrselect:inst58\|ctr7\[1\] " "Info: Duplicate register \"rrselect:inst58\|ctr7\[0\]\" merged to single register \"rrselect:inst58\|ctr7\[1\]\"" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rrselect:inst58\|ctr8\[0\] rrselect:inst58\|ctr8\[1\] " "Info: Duplicate register \"rrselect:inst58\|ctr8\[0\]\" merged to single register \"rrselect:inst58\|ctr8\[1\]\"" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rrselect:inst58\|ctr9\[0\] rrselect:inst58\|ctr9\[1\] " "Info: Duplicate register \"rrselect:inst58\|ctr9\[0\]\" merged to single register \"rrselect:inst58\|ctr9\[1\]\"" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rrselect:inst58\|ctr10\[0\] rrselect:inst58\|ctr10\[1\] " "Info: Duplicate register \"rrselect:inst58\|ctr10\[0\]\" merged to single register \"rrselect:inst58\|ctr10\[1\]\"" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rrselect:inst58\|ctr11\[0\] rrselect:inst58\|ctr11\[1\] " "Info: Duplicate register \"rrselect:inst58\|ctr11\[0\]\" merged to single register \"rrselect:inst58\|ctr11\[1\]\"" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rrselect:inst58\|ctr12\[0\] rrselect:inst58\|ctr12\[1\] " "Info: Duplicate register \"rrselect:inst58\|ctr12\[0\]\" merged to single register \"rrselect:inst58\|ctr12\[1\]\"" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rrselect:inst58\|ctr13\[0\] rrselect:inst58\|ctr13\[1\] " "Info: Duplicate register \"rrselect:inst58\|ctr13\[0\]\" merged to single register \"rrselect:inst58\|ctr13\[1\]\"" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rrselect:inst58\|ctr14\[0\] rrselect:inst58\|ctr14\[1\] " "Info: Duplicate register \"rrselect:inst58\|ctr14\[0\]\" merged to single register \"rrselect:inst58\|ctr14\[1\]\"" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "bslect:inst60\|ctr15\[0\] data_in GND " "Warning (14130): Reduced register \"bslect:inst60\|ctr15\[0\]\" with stuck data_in port to stuck value GND" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "bslect:inst60\|ctr4\[1\] data_in GND " "Warning (14130): Reduced register \"bslect:inst60\|ctr4\[1\]\" with stuck data_in port to stuck value GND" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
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