prev_cmp_ctr.map.qmsg

pwm控制模块 使用过很多次

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 21 17:07:01 2008 " "Info: Processing started: Fri Nov 21 17:07:01 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ctr -c ctr " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ctr -c ctr" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/ctr1.vhd " "Warning: Can't analyze file -- file F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/ctr1.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div-ddiv " "Info: Found design unit 1: div-ddiv" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 div " "Info: Found entity 1: div" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file key.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 key-kkey " "Info: Found design unit 1: key-kkey" {  } { { "key.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/key.vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 key " "Info: Found entity 1: key" {  } { { "key.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/key.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fenpin.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fenpin.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fenpin-fen " "Info: Found design unit 1: fenpin-fen" {  } { { "fenpin.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/fenpin.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 fenpin " "Info: Found entity 1: fenpin" {  } { { "fenpin.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/fenpin.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "slect.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file slect.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rslect-rsle " "Info: Found design unit 1: rslect-rsle" {  } { { "slect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/slect.vhd" 64 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 rslect " "Info: Found entity 1: rslect" {  } { { "slect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/slect.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rr.vhd " "Warning: Can't analyze file -- file F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rr.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rslect.vhd " "Warning: Can't analyze file -- file F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rslect.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gslect.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file gslect.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 gslect-rsle " "Info: Found design unit 1: gslect-rsle" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 30 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 gslect " "Info: Found entity 1: gslect" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bslect.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file bslect.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bslect-rsle " "Info: Found design unit 1: bslect-rsle" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 30 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 bslect " "Info: Found entity 1: bslect" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ctr.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ctr.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ctr " "Info: Found entity 1: ctr" {  } { { "ctr.bdf" "" { Schematic "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/ctr.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rselect.vhd " "Warning: Can't analyze file -- file F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rselect.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rrselect.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rrselect.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rrselect-rsle " "Info: Found design unit 1: rrselect-rsle" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 30 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 rrselect " "Info: Found entity 1: rrselect" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "colour.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file colour.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 colour-clr " "Info: Found design unit 1: colour-clr" {  } { { "colour.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/colour.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 colour " "Info: Found entity 1: colour" {  } { { "colour.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/colour.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/dd.vhd " "Warning: Can't analyze file -- file F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/dd.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file test.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 test-rsle " "Info: Found design unit 1: test-rsle" {  } { { "test.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/test.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 test " "Info: Found entity 1: test" {  } { { "test.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/test.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}