prev_cmp_ctr.tan.qmsg

pwm控制模块 使用过很多次

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "key:inst2\|keyout2 " "Info: Detected ripple clock \"key:inst2\|keyout2\" as buffer" {  } { { "key.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/key.vhd" 12 -1 0 } } { "d:/quartus/quar/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus/quar/quartus/bin/Assignment Editor.qase" 1 { { 0 "key:inst2\|keyout2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "key:inst2\|keyout1 " "Info: Detected ripple clock \"key:inst2\|keyout1\" as buffer" {  } { { "key.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/key.vhd" 11 -1 0 } } { "d:/quartus/quar/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus/quar/quartus/bin/Assignment Editor.qase" 1 { { 0 "key:inst2\|keyout1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "key:inst2\|keyout3 " "Info: Detected ripple clock \"key:inst2\|keyout3\" as buffer" {  } { { "key.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/key.vhd" 13 -1 0 } } { "d:/quartus/quar/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus/quar/quartus/bin/Assignment Editor.qase" 1 { { 0 "key:inst2\|keyout3" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst1\|temp " "Info: Detected ripple clock \"fenpin:inst1\|temp\" as buffer" {  } { { "fenpin.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/fenpin.vhd" 21 -1 0 } } { "d:/quartus/quar/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus/quar/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst1\|temp" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register div:inst48\|cnt\[2\] register div:inst21\|pwm 234.85 MHz 4.258 ns Internal " "Info: Clock \"clk\" has Internal fmax of 234.85 MHz between source register \"div:inst48\|cnt\[2\]\" and destination register \"div:inst21\|pwm\" (period= 4.258 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.036 ns + Longest register register " "Info: + Longest register to register delay is 4.036 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div:inst48\|cnt\[2\] 1 REG LCFF_X21_Y8_N13 52 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y8_N13; Fanout = 52; REG Node = 'div:inst48\|cnt\[2\]'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "" { div:inst48|cnt[2] } "NODE_NAME" } } { "div.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.672 ns) + CELL(0.388 ns) 2.060 ns div:inst21\|LessThan0~275 2 COMB LCCOMB_X8_Y9_N18 1 " "Info: 2: + IC(1.672 ns) + CELL(0.388 ns) = 2.060 ns; Loc. = LCCOMB_X8_Y9_N18; Fanout = 1; COMB Node = 'div:inst21\|LessThan0~275'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "2.060 ns" { div:inst48|cnt[2] div:inst21|LessThan0~275 } "NODE_NAME" } } { "div.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/div.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.250 ns) + CELL(0.150 ns) 2.460 ns div:inst21\|LessThan0~276 3 COMB LCCOMB_X8_Y9_N6 1 " "Info: 3: + IC(0.250 ns) + CELL(0.150 ns) = 2.460 ns; Loc. = LCCOMB_X8_Y9_N6; Fanout = 1; COMB Node = 'div:inst21\|LessThan0~276'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { div:inst21|LessThan0~275 div:inst21|LessThan0~276 } "NODE_NAME" } } { "div.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/div.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.250 ns) + CELL(0.150 ns) 2.860 ns div:inst21\|LessThan0~277 4 COMB LCCOMB_X8_Y9_N20 1 " "Info: 4: + IC(0.250 ns) + CELL(0.150 ns) = 2.860 ns; Loc. = LCCOMB_X8_Y9_N20; Fanout = 1; COMB Node = 'div:inst21\|LessThan0~277'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { div:inst21|LessThan0~276 div:inst21|LessThan0~277 } "NODE_NAME" } } { "div.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/div.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.942 ns) + CELL(0.150 ns) 3.952 ns div:inst21\|LessThan0~278 5 COMB LCCOMB_X14_Y9_N18 1 " "Info: 5: + IC(0.942 ns) + CELL(0.150 ns) = 3.952 ns; Loc. = LCCOMB_X14_Y9_N18; Fanout = 1; COMB Node = 'div:inst21\|LessThan0~278'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "1.092 ns" { div:inst21|LessThan0~277 div:inst21|LessThan0~278 } "NODE_NAME" } } { "div.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/div.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 4.036 ns div:inst21\|pwm 6 REG LCFF_X14_Y9_N19 1 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 4.036 ns; Loc. = LCFF_X14_Y9_N19; Fanout = 1; REG Node = 'div:inst21\|pwm'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { div:inst21|LessThan0~278 div:inst21|pwm } "NODE_NAME" } } { "div.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/div.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.922 ns ( 22.84 % ) " "Info: Total cell delay = 0.922 ns ( 22.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.114 ns ( 77.16 % ) " "Info: Total interconnect delay = 3.114 ns ( 77.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "4.036 ns" { div:inst48|cnt[2] div:inst21|LessThan0~275 div:inst21|LessThan0~276 div:inst21|LessThan0~277 div:inst21|LessThan0~278 div:inst21|pwm } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "4.036 ns" { div:inst48|cnt[2] {} div:inst21|LessThan0~275 {} div:inst21|LessThan0~276 {} div:inst21|LessThan0~277 {} div:inst21|LessThan0~278 {} div:inst21|pwm {} } { 0.000ns 1.672ns 0.250ns 0.250ns 0.942ns 0.000ns } { 0.000ns 0.388ns 0.150ns 0.150ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.008 ns - Smallest " "Info: - Smallest clock skew is -0.008 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 4.974 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 4.974 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ctr.bdf" "" { Schematic "F:/work/project/circuit/FPGA/ctr_rev/ctr.bdf" { { -32 24 192 -16 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.331 ns) + CELL(0.787 ns) 2.107 ns fenpin:inst1\|temp 2 REG LCFF_X1_Y6_N15 5 " "Info: 2: + IC(0.331 ns) + CELL(0.787 ns) = 2.107 ns; Loc. = LCFF_X1_Y6_N15; Fanout = 5; REG Node = 'fenpin:inst1\|temp'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "1.118 ns" { clk fenpin:inst1|temp } "NODE_NAME" } } { "fenpin.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/fenpin.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.628 ns) + CELL(0.000 ns) 3.735 ns fenpin:inst1\|temp~clkctrl 3 COMB CLKCTRL_G0 79 " "Info: 3: + IC(1.628 ns) + CELL(0.000 ns) = 3.735 ns; Loc. = CLKCTRL_G0; Fanout = 79; COMB Node = 'fenpin:inst1\|temp~clkctrl'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "1.628 ns" { fenpin:inst1|temp fenpin:inst1|temp~clkctrl } "NODE_NAME" } } { "fenpin.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/fenpin.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.702 ns) + CELL(0.537 ns) 4.974 ns div:inst21\|pwm 4 REG LCFF_X14_Y9_N19 1 " "Info: 4: + IC(0.702 ns) + CELL(0.537 ns) = 4.974 ns; Loc. = LCFF_X14_Y9_N19; Fanout = 1; REG Node = 'div:inst21\|pwm'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "1.239 ns" { fenpin:inst1|temp~clkctrl div:inst21|pwm } "NODE_NAME" } } { "div.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/div.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.313 ns ( 46.50 % ) " "Info: Total cell delay = 2.313 ns ( 46.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.661 ns ( 53.50 % ) " "Info: Total interconnect delay = 2.661 ns ( 53.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "4.974 ns" { clk fenpin:inst1|temp fenpin:inst1|temp~clkctrl div:inst21|pwm } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "4.974 ns" { clk {} clk~combout {} fenpin:inst1|temp {} fenpin:inst1|temp~clkctrl {} div:inst21|pwm {} } { 0.000ns 0.000ns 0.331ns 1.628ns 0.702ns } { 0.000ns 0.989ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.982 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 4.982 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ctr.bdf" "" { Schematic "F:/work/project/circuit/FPGA/ctr_rev/ctr.bdf" { { -32 24 192 -16 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.331 ns) + CELL(0.787 ns) 2.107 ns fenpin:inst1\|temp 2 REG LCFF_X1_Y6_N15 5 " "Info: 2: + IC(0.331 ns) + CELL(0.787 ns) = 2.107 ns; Loc. = LCFF_X1_Y6_N15; Fanout = 5; REG Node = 'fenpin:inst1\|temp'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "1.118 ns" { clk fenpin:inst1|temp } "NODE_NAME" } } { "fenpin.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/fenpin.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.628 ns) + CELL(0.000 ns) 3.735 ns fenpin:inst1\|temp~clkctrl 3 COMB CLKCTRL_G0 79 " "Info: 3: + IC(1.628 ns) + CELL(0.000 ns) = 3.735 ns; Loc. = CLKCTRL_G0; Fanout = 79; COMB Node = 'fenpin:inst1\|temp~clkctrl'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "1.628 ns" { fenpin:inst1|temp fenpin:inst1|temp~clkctrl } "NODE_NAME" } } { "fenpin.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/fenpin.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.710 ns) + CELL(0.537 ns) 4.982 ns div:inst48\|cnt\[2\] 4 REG LCFF_X21_Y8_N13 52 " "Info: 4: + IC(0.710 ns) + CELL(0.537 ns) = 4.982 ns; Loc. = LCFF_X21_Y8_N13; Fanout = 52; REG Node = 'div:inst48\|cnt\[2\]'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "1.247 ns" { fenpin:inst1|temp~clkctrl div:inst48|cnt[2] } "NODE_NAME" } } { "div.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.313 ns ( 46.43 % ) " "Info: Total cell delay = 2.313 ns ( 46.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.669 ns ( 53.57 % ) " "Info: Total interconnect delay = 2.669 ns ( 53.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "4.982 ns" { clk fenpin:inst1|temp fenpin:inst1|temp~clkctrl div:inst48|cnt[2] } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "4.982 ns" { clk {} clk~combout {} fenpin:inst1|temp {} fenpin:inst1|temp~clkctrl {} div:inst48|cnt[2] {} } { 0.000ns 0.000ns 0.331ns 1.628ns 0.710ns } { 0.000ns 0.989ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "4.974 ns" { clk fenpin:inst1|temp fenpin:inst1|temp~clkctrl div:inst21|pwm } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "4.974 ns" { clk {} clk~combout {} fenpin:inst1|temp {} fenpin:inst1|temp~clkctrl {} div:inst21|pwm {} } { 0.000ns 0.000ns 0.331ns 1.628ns 0.702ns } { 0.000ns 0.989ns 0.787ns 0.000ns 0.537ns } "" } } { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "4.982 ns" { clk fenpin:inst1|temp fenpin:inst1|temp~clkctrl div:inst48|cnt[2] } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "4.982 ns" { clk {} clk~combout {} fenpin:inst1|temp {} fenpin:inst1|temp~clkctrl {} div:inst48|cnt[2] {} } { 0.000ns 0.000ns 0.331ns 1.628ns 0.710ns } { 0.000ns 0.989ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "div.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/div.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "div.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/div.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "4.036 ns" { div:inst48|cnt[2] div:inst21|LessThan0~275 div:inst21|LessThan0~276 div:inst21|LessThan0~277 div:inst21|LessThan0~278 div:inst21|pwm } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "4.036 ns" { div:inst48|cnt[2] {} div:inst21|LessThan0~275 {} div:inst21|LessThan0~276 {} div:inst21|LessThan0~277 {} div:inst21|LessThan0~278 {} div:inst21|pwm {} } { 0.000ns 1.672ns 0.250ns 0.250ns 0.942ns 0.000ns } { 0.000ns 0.388ns 0.150ns 0.150ns 0.150ns 0.084ns } "" } } { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "4.974 ns" { clk fenpin:inst1|temp fenpin:inst1|temp~clkctrl div:inst21|pwm } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "4.974 ns" { clk {} clk~combout {} fenpin:inst1|temp {} fenpin:inst1|temp~clkctrl {} div:inst21|pwm {} } { 0.000ns 0.000ns 0.331ns 1.628ns 0.702ns } { 0.000ns 0.989ns 0.787ns 0.000ns 0.537ns } "" } } { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "4.982 ns" { clk fenpin:inst1|temp fenpin:inst1|temp~clkctrl div:inst48|cnt[2] } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "4.982 ns" { clk {} clk~combout {} fenpin:inst1|temp {} fenpin:inst1|temp~clkctrl {} div:inst48|cnt[2] {} } { 0.000ns 0.000ns 0.331ns 1.628ns 0.710ns } { 0.000ns 0.989ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "key:inst2\|keyout1 key1 clk 3.443 ns register " "Info: tsu for register \"key:inst2\|keyout1\" (data pin = \"key1\", clock pin = \"clk\") is 3.443 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.560 ns + Longest pin register " "Info: + Longest pin to register delay is 6.560 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns key1 1 PIN PIN_4 8 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_4; Fanout = 8; PIN Node = 'key1'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "" { key1 } "NODE_NAME" } } { "ctr.bdf" "" { Schematic "F:/work/project/circuit/FPGA/ctr_rev/ctr.bdf" { { 456 32 200 472 "key1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.243 ns) + CELL(0.371 ns) 6.476 ns key:inst2\|keyout1~15 2 COMB LCCOMB_X2_Y6_N24 1 " "Info: 2: + IC(5.243 ns) + CELL(0.371 ns) = 6.476 ns; Loc. = LCCOMB_X2_Y6_N24; Fanout = 1; COMB Node = 'key:inst2\|keyout1~15'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "5.614 ns" { key1 key:inst2|keyout1~15 } "NODE_NAME" } } { "key.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/key.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.560 ns key:inst2\|keyout1 3 REG LCFF_X2_Y6_N25 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.560 ns; Loc. = LCFF_X2_Y6_N25; Fanout = 1; REG Node = 'key:inst2\|keyout1'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { key:inst2|keyout1~15 key:inst2|keyout1 } "NODE_NAME" } } { "key.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/key.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.317 ns ( 20.08 % ) " "Info: Total cell delay = 1.317 ns ( 20.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.243 ns ( 79.92 % ) " "Info: Total interconnect delay = 5.243 ns ( 79.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "6.560 ns" { key1 key:inst2|keyout1~15 key:inst2|keyout1 } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "6.560 ns" { key1 {} key1~combout {} key:inst2|keyout1~15 {} key:inst2|keyout1 {} } { 0.000ns 0.000ns 5.243ns 0.000ns } { 0.000ns 0.862ns 0.371ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "key.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/key.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.081 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.081 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ctr.bdf" "" { Schematic "F:/work/project/circuit/FPGA/ctr_rev/ctr.bdf" { { -32 24 192 -16 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.331 ns) + CELL(0.787 ns) 2.107 ns fenpin:inst1\|temp 2 REG LCFF_X1_Y6_N15 5 " "Info: 2: + IC(0.331 ns) + CELL(0.787 ns) = 2.107 ns; Loc. = LCFF_X1_Y6_N15; Fanout = 5; REG Node = 'fenpin:inst1\|temp'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "1.118 ns" { clk fenpin:inst1|temp } "NODE_NAME" } } { "fenpin.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/fenpin.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.537 ns) 3.081 ns key:inst2\|keyout1 3 REG LCFF_X2_Y6_N25 1 " "Info: 3: + IC(0.437 ns) + CELL(0.537 ns) = 3.081 ns; Loc. = LCFF_X2_Y6_N25; Fanout = 1; REG Node = 'key:inst2\|keyout1'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "0.974 ns" { fenpin:inst1|temp key:inst2|keyout1 } "NODE_NAME" } } { "key.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/key.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.313 ns ( 75.07 % ) " "Info: Total cell delay = 2.313 ns ( 75.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.768 ns ( 24.93 % ) " "Info: Total interconnect delay = 0.768 ns ( 24.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "3.081 ns" { clk fenpin:inst1|temp key:inst2|keyout1 } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "3.081 ns" { clk {} clk~combout {} fenpin:inst1|temp {} key:inst2|keyout1 {} } { 0.000ns 0.000ns 0.331ns 0.437ns } { 0.000ns 0.989ns 0.787ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "6.560 ns" { key1 key:inst2|keyout1~15 key:inst2|keyout1 } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "6.560 ns" { key1 {} key1~combout {} key:inst2|keyout1~15 {} key:inst2|keyout1 {} } { 0.000ns 0.000ns 5.243ns 0.000ns } { 0.000ns 0.862ns 0.371ns 0.084ns } "" } } { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "3.081 ns" { clk fenpin:inst1|temp key:inst2|keyout1 } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "3.081 ns" { clk {} clk~combout {} fenpin:inst1|temp {} key:inst2|keyout1 {} } { 0.000ns 0.000ns 0.331ns 0.437ns } { 0.000ns 0.989ns 0.787ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk R_PWM10 div:inst13\|pwm 10.371 ns register " "Info: tco from clock \"clk\" to destination pin \"R_PWM10\" through register \"div:inst13\|pwm\" is 10.371 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.978 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 4.978 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ctr.bdf" "" { Schematic "F:/work/project/circuit/FPGA/ctr_rev/ctr.bdf" { { -32 24 192 -16 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.331 ns) + CELL(0.787 ns) 2.107 ns fenpin:inst1\|temp 2 REG LCFF_X1_Y6_N15 5 " "Info: 2: + IC(0.331 ns) + CELL(0.787 ns) = 2.107 ns; Loc. = LCFF_X1_Y6_N15; Fanout = 5; REG Node = 'fenpin:inst1\|temp'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "1.118 ns" { clk fenpin:inst1|temp } "NODE_NAME" } } { "fenpin.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/fenpin.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.628 ns) + CELL(0.000 ns) 3.735 ns fenpin:inst1\|temp~clkctrl 3 COMB CLKCTRL_G0 79 " "Info: 3: + IC(1.628 ns) + CELL(0.000 ns) = 3.735 ns; Loc. = CLKCTRL_G0; Fanout = 79; COMB Node = 'fenpin:inst1\|temp~clkctrl'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "1.628 ns" { fenpin:inst1|temp fenpin:inst1|temp~clkctrl } "NODE_NAME" } } { "fenpin.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/fenpin.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.706 ns) + CELL(0.537 ns) 4.978 ns div:inst13\|pwm 4 REG LCFF_X20_Y5_N11 1 " "Info: 4: + IC(0.706 ns) + CELL(0.537 ns) = 4.978 ns; Loc. = LCFF_X20_Y5_N11; Fanout = 1; REG Node = 'div:inst13\|pwm'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "1.243 ns" { fenpin:inst1|temp~clkctrl div:inst13|pwm } "NODE_NAME" } } { "div.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/div.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.313 ns ( 46.46 % ) " "Info: Total cell delay = 2.313 ns ( 46.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.665 ns ( 53.54 % ) " "Info: Total interconnect delay = 2.665 ns ( 53.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "4.978 ns" { clk fenpin:inst1|temp fenpin:inst1|temp~clkctrl div:inst13|pwm } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "4.978 ns" { clk {} clk~combout {} fenpin:inst1|temp {} fenpin:inst1|temp~clkctrl {} div:inst13|pwm {} } { 0.000ns 0.000ns 0.331ns 1.628ns 0.706ns } { 0.000ns 0.989ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "div.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/div.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.143 ns + Longest register pin " "Info: + Longest register to pin delay is 5.143 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div:inst13\|pwm 1 REG LCFF_X20_Y5_N11 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y5_N11; Fanout = 1; REG Node = 'div:inst13\|pwm'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "" { div:inst13|pwm } "NODE_NAME" } } { "div.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/div.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.345 ns) + CELL(2.798 ns) 5.143 ns R_PWM10 2 PIN PIN_136 0 " "Info: 2: + IC(2.345 ns) + CELL(2.798 ns) = 5.143 ns; Loc. = PIN_136; Fanout = 0; PIN Node = 'R_PWM10'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "5.143 ns" { div:inst13|pwm R_PWM10 } "NODE_NAME" } } { "ctr.bdf" "" { Schematic "F:/work/project/circuit/FPGA/ctr_rev/ctr.bdf" { { -912 1616 1792 -896 "R_PWM10" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.798 ns ( 54.40 % ) " "Info: Total cell delay = 2.798 ns ( 54.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.345 ns ( 45.60 % ) " "Info: Total interconnect delay = 2.345 ns ( 45.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "5.143 ns" { div:inst13|pwm R_PWM10 } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "5.143 ns" { div:inst13|pwm {} R_PWM10 {} } { 0.000ns 2.345ns } { 0.000ns 2.798ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "4.978 ns" { clk fenpin:inst1|temp fenpin:inst1|temp~clkctrl div:inst13|pwm } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "4.978 ns" { clk {} clk~combout {} fenpin:inst1|temp {} fenpin:inst1|temp~clkctrl {} div:inst13|pwm {} } { 0.000ns 0.000ns 0.331ns 1.628ns 0.706ns } { 0.000ns 0.989ns 0.787ns 0.000ns 0.537ns } "" } } { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "5.143 ns" { div:inst13|pwm R_PWM10 } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "5.143 ns" { div:inst13|pwm {} R_PWM10 {} } { 0.000ns 2.345ns } { 0.000ns 2.798ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}