ctr.tan.qmsg

pwm控制模块 使用过很多次

{ "Info" "ITDB_TH_RESULT" "key:inst2\|key_cnt2\[6\] key2 clk -1.085 ns register " "Info: th for register \"key:inst2\|key_cnt2\[6\]\" (data pin = \"key2\", clock pin = \"clk\") is -1.085 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 4.957 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 4.957 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ctr.bdf" "" { Schematic "F:/work/project/circuit/FPGA/ctr_rev/ctr.bdf" { { -32 24 192 -16 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.331 ns) + CELL(0.787 ns) 2.107 ns fenpin:inst1\|temp 2 REG LCFF_X1_Y6_N15 5 " "Info: 2: + IC(0.331 ns) + CELL(0.787 ns) = 2.107 ns; Loc. = LCFF_X1_Y6_N15; Fanout = 5; REG Node = 'fenpin:inst1\|temp'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "1.118 ns" { clk fenpin:inst1|temp } "NODE_NAME" } } { "fenpin.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/fenpin.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.628 ns) + CELL(0.000 ns) 3.735 ns fenpin:inst1\|temp~clkctrl 3 COMB CLKCTRL_G0 79 " "Info: 3: + IC(1.628 ns) + CELL(0.000 ns) = 3.735 ns; Loc. = CLKCTRL_G0; Fanout = 79; COMB Node = 'fenpin:inst1\|temp~clkctrl'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "1.628 ns" { fenpin:inst1|temp fenpin:inst1|temp~clkctrl } "NODE_NAME" } } { "fenpin.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/fenpin.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.685 ns) + CELL(0.537 ns) 4.957 ns key:inst2\|key_cnt2\[6\] 4 REG LCFF_X2_Y6_N21 2 " "Info: 4: + IC(0.685 ns) + CELL(0.537 ns) = 4.957 ns; Loc. = LCFF_X2_Y6_N21; Fanout = 2; REG Node = 'key:inst2\|key_cnt2\[6\]'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "1.222 ns" { fenpin:inst1|temp~clkctrl key:inst2|key_cnt2[6] } "NODE_NAME" } } { "key.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/key.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.313 ns ( 46.66 % ) " "Info: Total cell delay = 2.313 ns ( 46.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.644 ns ( 53.34 % ) " "Info: Total interconnect delay = 2.644 ns ( 53.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "4.957 ns" { clk fenpin:inst1|temp fenpin:inst1|temp~clkctrl key:inst2|key_cnt2[6] } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "4.957 ns" { clk {} clk~combout {} fenpin:inst1|temp {} fenpin:inst1|temp~clkctrl {} key:inst2|key_cnt2[6] {} } { 0.000ns 0.000ns 0.331ns 1.628ns 0.685ns } { 0.000ns 0.989ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "key.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/key.vhd" 43 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.308 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.308 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns key2 1 PIN PIN_24 8 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_24; Fanout = 8; PIN Node = 'key2'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "" { key2 } "NODE_NAME" } } { "ctr.bdf" "" { Schematic "F:/work/project/circuit/FPGA/ctr_rev/ctr.bdf" { { 480 32 200 496 "key2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.946 ns) + CELL(0.510 ns) 6.308 ns key:inst2\|key_cnt2\[6\] 2 REG LCFF_X2_Y6_N21 2 " "Info: 2: + IC(4.946 ns) + CELL(0.510 ns) = 6.308 ns; Loc. = LCFF_X2_Y6_N21; Fanout = 2; REG Node = 'key:inst2\|key_cnt2\[6\]'" {  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "5.456 ns" { key2 key:inst2|key_cnt2[6] } "NODE_NAME" } } { "key.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/key.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.362 ns ( 21.59 % ) " "Info: Total cell delay = 1.362 ns ( 21.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.946 ns ( 78.41 % ) " "Info: Total interconnect delay = 4.946 ns ( 78.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "6.308 ns" { key2 key:inst2|key_cnt2[6] } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "6.308 ns" { key2 {} key2~combout {} key:inst2|key_cnt2[6] {} } { 0.000ns 0.000ns 4.946ns } { 0.000ns 0.852ns 0.510ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "4.957 ns" { clk fenpin:inst1|temp fenpin:inst1|temp~clkctrl key:inst2|key_cnt2[6] } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "4.957 ns" { clk {} clk~combout {} fenpin:inst1|temp {} fenpin:inst1|temp~clkctrl {} key:inst2|key_cnt2[6] {} } { 0.000ns 0.000ns 0.331ns 1.628ns 0.685ns } { 0.000ns 0.989ns 0.787ns 0.000ns 0.537ns } "" } } { "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quar/quartus/bin/TimingClosureFloorplan.fld" "" "6.308 ns" { key2 key:inst2|key_cnt2[6] } "NODE_NAME" } } { "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quar/quartus/bin/Technology_Viewer.qrui" "6.308 ns" { key2 {} key2~combout {} key:inst2|key_cnt2[6] {} } { 0.000ns 0.000ns 4.946ns } { 0.000ns 0.852ns 0.510ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "120 " "Info: Allocated 120 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 18 15:34:48 2008 " "Info: Processing ended: Thu Sep 18 15:34:48 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}