ctr.map.qmsg

pwm控制模块 使用过很多次

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "gslect:inst59\|ctr11\[1\] data_in GND " "Warning (14130): Reduced register \"gslect:inst59\|ctr11\[1\]\" with stuck data_in port to stuck value GND" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "gslect:inst59\|ctr12\[1\] data_in GND " "Warning (14130): Reduced register \"gslect:inst59\|ctr12\[1\]\" with stuck data_in port to stuck value GND" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "gslect:inst59\|ctr13\[1\] data_in GND " "Warning (14130): Reduced register \"gslect:inst59\|ctr13\[1\]\" with stuck data_in port to stuck value GND" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "gslect:inst59\|ctr14\[1\] data_in GND " "Warning (14130): Reduced register \"gslect:inst59\|ctr14\[1\]\" with stuck data_in port to stuck value GND" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rrselect:inst58\|ctr15\[0\] data_in GND " "Warning (14130): Reduced register \"rrselect:inst58\|ctr15\[0\]\" with stuck data_in port to stuck value GND" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rrselect:inst58\|ctr4\[1\] data_in GND " "Warning (14130): Reduced register \"rrselect:inst58\|ctr4\[1\]\" with stuck data_in port to stuck value GND" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rrselect:inst58\|ctr5\[1\] data_in GND " "Warning (14130): Reduced register \"rrselect:inst58\|ctr5\[1\]\" with stuck data_in port to stuck value GND" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rrselect:inst58\|ctr6\[1\] data_in GND " "Warning (14130): Reduced register \"rrselect:inst58\|ctr6\[1\]\" with stuck data_in port to stuck value GND" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rrselect:inst58\|ctr7\[1\] data_in GND " "Warning (14130): Reduced register \"rrselect:inst58\|ctr7\[1\]\" with stuck data_in port to stuck value GND" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rrselect:inst58\|ctr8\[1\] data_in GND " "Warning (14130): Reduced register \"rrselect:inst58\|ctr8\[1\]\" with stuck data_in port to stuck value GND" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rrselect:inst58\|ctr9\[1\] data_in GND " "Warning (14130): Reduced register \"rrselect:inst58\|ctr9\[1\]\" with stuck data_in port to stuck value GND" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rrselect:inst58\|ctr10\[1\] data_in GND " "Warning (14130): Reduced register \"rrselect:inst58\|ctr10\[1\]\" with stuck data_in port to stuck value GND" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rrselect:inst58\|ctr11\[1\] data_in GND " "Warning (14130): Reduced register \"rrselect:inst58\|ctr11\[1\]\" with stuck data_in port to stuck value GND" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rrselect:inst58\|ctr12\[1\] data_in GND " "Warning (14130): Reduced register \"rrselect:inst58\|ctr12\[1\]\" with stuck data_in port to stuck value GND" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rrselect:inst58\|ctr13\[1\] data_in GND " "Warning (14130): Reduced register \"rrselect:inst58\|ctr13\[1\]\" with stuck data_in port to stuck value GND" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rrselect:inst58\|ctr14\[1\] data_in GND " "Warning (14130): Reduced register \"rrselect:inst58\|ctr14\[1\]\" with stuck data_in port to stuck value GND" {  } { { "rrselect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/rrselect.vhd" 68 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst12\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst12\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst22\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst22\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst32\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst32\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst42\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst42\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst13\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst13\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst23\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst23\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst33\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst33\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst43\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst43\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst14\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst14\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst24\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst24\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst34\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst34\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst44\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst44\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst4\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst4\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst15\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst15\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst25\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst25\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst35\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst35\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst45\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst45\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst5\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst5\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst16\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst16\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst26\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst26\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst36\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst36\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst46\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst46\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst56\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst56\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst6\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst6\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst17\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst17\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst27\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst27\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst37\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst37\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst47\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst47\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst57\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst57\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst7\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst7\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst18\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst18\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst28\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst28\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst38\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst38\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst8\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst8\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst19\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst19\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst29\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst29\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst39\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst39\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst9\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst9\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst\|cnt\[4\] div:inst48\|cnt\[4\] " "Info: Duplicate register \"div:inst\|cnt\[4\]\" merged to single register \"div:inst48\|cnt\[4\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div:inst12\|cnt\[3\] div:inst48\|cnt\[3\] " "Info: Duplicate register \"div:inst12\|cnt\[3\]\" merged to single register \"div:inst48\|cnt\[3\]\"" {  } { { "div.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/div.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_R