ctr.map.qmsg

pwm控制模块 使用过很多次

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tt.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file tt.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tt-rsle " "Info: Found design unit 1: tt-rsle" {  } { { "tt.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/tt.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 tt " "Info: Found entity 1: tt" {  } { { "tt.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/tt.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ctr " "Info: Elaborating entity \"ctr\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div div:inst " "Info: Elaborating entity \"div\" for hierarchy \"div:inst\"" {  } { { "ctr.bdf" "inst" { Schematic "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/ctr.bdf" { { -1888 1416 1528 -1792 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenpin fenpin:inst1 " "Info: Elaborating entity \"fenpin\" for hierarchy \"fenpin:inst1\"" {  } { { "ctr.bdf" "inst1" { Schematic "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/ctr.bdf" { { -56 272 392 40 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rrselect rrselect:inst58 " "Info: Elaborating entity \"rrselect\" for hierarchy \"rrselect:inst58\"" {  } { { "ctr.bdf" "inst58" { Schematic "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/ctr.bdf" { { -1240 792 976 -920 "inst58" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "key key:inst2 " "Info: Elaborating entity \"key\" for hierarchy \"key:inst2\"" {  } { { "ctr.bdf" "inst2" { Schematic "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/ctr.bdf" { { 416 272 400 544 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "colour colour:inst61 " "Info: Elaborating entity \"colour\" for hierarchy \"colour:inst61\"" {  } { { "ctr.bdf" "inst61" { Schematic "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/ctr.bdf" { { 256 440 568 352 "inst61" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "gslect gslect:inst59 " "Info: Elaborating entity \"gslect\" for hierarchy \"gslect:inst59\"" {  } { { "ctr.bdf" "inst59" { Schematic "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/ctr.bdf" { { 472 792 976 792 "inst59" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bslect bslect:inst60 " "Info: Elaborating entity \"bslect\" for hierarchy \"bslect:inst60\"" {  } { { "ctr.bdf" "inst60" { Schematic "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/ctr.bdf" { { 2312 808 992 2632 "inst60" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "bslect:inst60\|ctr0\[1\] data_in GND " "Warning (14130): Reduced register \"bslect:inst60\|ctr0\[1\]\" with stuck data_in port to stuck value GND" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "bslect:inst60\|ctr0\[0\] data_in GND " "Warning (14130): Reduced register \"bslect:inst60\|ctr0\[0\]\" with stuck data_in port to stuck value GND" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "bslect:inst60\|ctr1\[1\] data_in GND " "Warning (14130): Reduced register \"bslect:inst60\|ctr1\[1\]\" with stuck data_in port to stuck value GND" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "bslect:inst60\|ctr1\[0\] data_in GND " "Warning (14130): Reduced register \"bslect:inst60\|ctr1\[0\]\" with stuck data_in port to stuck value GND" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "bslect:inst60\|ctr2\[1\] data_in GND " "Warning (14130): Reduced register \"bslect:inst60\|ctr2\[1\]\" with stuck data_in port to stuck value GND" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "bslect:inst60\|ctr2\[0\] data_in GND " "Warning (14130): Reduced register \"bslect:inst60\|ctr2\[0\]\" with stuck data_in port to stuck value GND" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "bslect:inst60\|ctr3\[1\] data_in GND " "Warning (14130): Reduced register \"bslect:inst60\|ctr3\[1\]\" with stuck data_in port to stuck value GND" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "bslect:inst60\|ctr3\[0\] data_in GND " "Warning (14130): Reduced register \"bslect:inst60\|ctr3\[0\]\" with stuck data_in port to stuck value GND" {  } { { "bslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/bslect.vhd" 67 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "gslect:inst59\|ctr0\[1\] data_in GND " "Warning (14130): Reduced register \"gslect:inst59\|ctr0\[1\]\" with stuck data_in port to stuck value GND" {  } { { "gslect.vhd" "" { Text "F:/work/project/Circuit/FPGA/17_LED/ctr_rev_160us/gslect.vhd" 66 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}