prev_cmp_ctr.qmsg

pwm控制模块 使用过很多次

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 18 15:54:38 2008 " "Info: Processing started: Thu Sep 18 15:54:38 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ctr -c ctr --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ctr -c ctr --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/work/project/circuit/FPGA/ctr_rev/ctr1.vhd " "Warning: Can't analyze file -- file F:/work/project/circuit/FPGA/ctr_rev/ctr1.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div-ddiv " "Info: Found design unit 1: div-ddiv" {  } { { "div.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/div.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 div " "Info: Found entity 1: div" {  } { { "div.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/div.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file key.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 key-kkey " "Info: Found design unit 1: key-kkey" {  } { { "key.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/key.vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 key " "Info: Found entity 1: key" {  } { { "key.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/key.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fenpin.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fenpin.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fenpin-fen " "Info: Found design unit 1: fenpin-fen" {  } { { "fenpin.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/fenpin.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 fenpin " "Info: Found entity 1: fenpin" {  } { { "fenpin.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/fenpin.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "slect.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file slect.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rslect-rsle " "Info: Found design unit 1: rslect-rsle" {  } { { "slect.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/slect.vhd" 64 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 rslect " "Info: Found entity 1: rslect" {  } { { "slect.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/slect.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/work/project/circuit/FPGA/ctr_rev/rr.vhd " "Warning: Can't analyze file -- file F:/work/project/circuit/FPGA/ctr_rev/rr.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/work/project/circuit/FPGA/ctr_rev/rslect.vhd " "Warning: Can't analyze file -- file F:/work/project/circuit/FPGA/ctr_rev/rslect.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gslect.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file gslect.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 gslect-rsle " "Info: Found design unit 1: gslect-rsle" {  } { { "gslect.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/gslect.vhd" 30 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 gslect " "Info: Found entity 1: gslect" {  } { { "gslect.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/gslect.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bslect.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file bslect.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bslect-rsle " "Info: Found design unit 1: bslect-rsle" {  } { { "bslect.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/bslect.vhd" 30 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 bslect " "Info: Found entity 1: bslect" {  } { { "bslect.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/bslect.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ctr.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ctr.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ctr " "Info: Found entity 1: ctr" {  } { { "ctr.bdf" "" { Schematic "F:/work/project/circuit/FPGA/ctr_rev/ctr.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/work/project/circuit/FPGA/ctr_rev/rselect.vhd " "Warning: Can't analyze file -- file F:/work/project/circuit/FPGA/ctr_rev/rselect.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rrselect.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rrselect.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rrselect-rsle " "Info: Found design unit 1: rrselect-rsle" {  } { { "rrselect.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/rrselect.vhd" 30 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 rrselect " "Info: Found entity 1: rrselect" {  } { { "rrselect.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/rrselect.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "colour.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file colour.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 colour-clr " "Info: Found design unit 1: colour-clr" {  } { { "colour.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/colour.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 colour " "Info: Found entity 1: colour" {  } { { "colour.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/colour.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/work/project/circuit/FPGA/ctr_rev/dd.vhd " "Warning: Can't analyze file -- file F:/work/project/circuit/FPGA/ctr_rev/dd.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file test.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 test-rsle " "Info: Found design unit 1: test-rsle" {  } { { "test.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/test.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 test " "Info: Found entity 1: test" {  } { { "test.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/test.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tt.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file tt.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tt-rsle " "Info: Found design unit 1: tt-rsle" {  } { { "tt.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/tt.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 tt " "Info: Found entity 1: tt" {  } { { "tt.vhd" "" { Text "F:/work/project/circuit/FPGA/ctr_rev/tt.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ctr " "Info: Elaborating entity \"ctr\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div div:inst " "Info: Elaborating entity \"div\" for hierarchy \"div:inst\"" {  } { { "ctr.bdf" "inst" { Schematic "F:/work/project/circuit/FPGA/ctr_rev/ctr.bdf" { { -1888 1416 1528 -1792 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenpin fenpin:inst1 " "Info: Elaborating entity \"fenpin\" for hierarchy \"fenpin:inst1\"" {  } { { "ctr.bdf" "inst1" { Schematic "F:/work/project/circuit/FPGA/ctr_rev/ctr.bdf" { { -56 272 392 40 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rrselect rrselect:inst58 " "Info: Elaborating entity \"rrselect\" for hierarchy \"rrselect:inst58\"" {  } { { "ctr.bdf" "inst58" { Schematic "F:/work/project/circuit/FPGA/ctr_rev/ctr.bdf" { { -1240 792 976 -920 "inst58" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "key key:inst2 " "Info: Elaborating entity \"key\" for hierarchy \"key:inst2\"" {  } { { "ctr.bdf" "inst2" { Schematic "F:/work/project/circuit/FPGA/ctr_rev/ctr.bdf" { { 416 272 400 544 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "colour colour:inst61 " "Info: Elaborating entity \"colour\" for hierarchy \"colour:inst61\"" {  } { { "ctr.bdf" "inst61" { Schematic "F:/work/project/circuit/FPGA/ctr_rev/ctr.bdf" { { 256 440 568 352 "inst61" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "gslect gslect:inst59 " "Info: Elaborating entity \"gslect\" for hierarchy \"gslect:inst59\"" {  } { { "ctr.bdf" "inst59" { Schematic "F:/work/project/circuit/FPGA/ctr_rev/ctr.bdf" { { 472 792 976 792 "inst59" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bslect bslect:inst60 " "Info: Elaborating entity \"bslect\" for hierarchy \"bslect:inst60\"" {  } { { "ctr.bdf" "inst60" { Schematic "F:/work/project/circuit/FPGA/ctr_rev/ctr.bdf" { { 2312 808 992 2632 "inst60" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 5 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "160 " "Info: Allocated 160 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 18 15:54:51 2008 " "Info: Processing ended: Thu Sep 18 15:54:51 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}