fenpin.vhd

来自「pwm控制模块 使用过很多次」· VHDL 代码 · 共 32 行

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity fenpin is
port ( clk40m:in std_logic;
       clk10k:out std_logic
      );
end fenpin;



architecture fen of fenpin is
signal temp:std_logic;
signal cnt:integer range 0 to 39;
constant m:integer:=39;
begin
process(clk40m)
begin
if clk40m'event and clk40m='1' then
   if cnt=m then
      temp<=not temp;
      cnt<=0;
   else cnt<=cnt+1;
   end if;
end if;
end process;
clk10k<=temp;
end fen;