key.vhd

来自「pwm控制模块 使用过很多次」· VHDL 代码 · 共 78 行

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity key is
port ( clk10k:in std_logic;
       key1:in std_logic;
       key2:in std_logic;
       key3:in std_logic;
       keyout1:out std_logic;
       keyout2:out std_logic;
       keyout3:out std_logic  
      );
end key;


architecture kkey of key is

begin

process(clk10k)
variable key_cnt1:integer range 0 to 127;
begin
if clk10k'event and clk10k='1' then
   if key1='1' then
      key_cnt1:=0;
      keyout1<='0';
   else 
      if key_cnt1=127 then
           key_cnt1:=key_cnt1;
           keyout1<='1';
      else key_cnt1:=key_cnt1+1;
           keyout1<='0';
      end if;
   end if;
end if;
end process;

process(clk10k)
variable key_cnt2:integer range 0 to 127;
begin
if clk10k'event and clk10k='1' then
   if key2='1' then
      key_cnt2:=0;
      keyout2<='0';
   else 
      if key_cnt2=127 then
           key_cnt2:=key_cnt2;
           keyout2<='1';
      else key_cnt2:=key_cnt2+1;
           keyout2<='0';
      end if;
   end if;
end if;
end process;

process(clk10k)
variable key_cnt3:integer range 0 to 127;
begin
if clk10k'event and clk10k='1' then
   if key3='1' then
      key_cnt3:=0;
      keyout3<='0';
   else 
      if key_cnt3=127 then
           key_cnt3:=key_cnt3;
           keyout3<='1';
      else key_cnt3:=key_cnt3+1;
           keyout3<='0';
      end if;
   end if;
end if;
end process;

end kkey;