ad.asm

F740的程序 非常适合初学者

*                FEDCBA9876543210
* bit 15-12     0000:   CONV03 channel
* bit 11-8      0000:   CONV02 channel
* bit 7-4       0000:   CONV01 channel
* bit 3-0       0000:   CONV00 channel (only active conversion)

        SPLK    #0010000000010000b, ADCTRL1
*                ||||||||||||||||
*                FEDCBA9876543210
* bit 15        0:      reserved
* bit 14        0:      RESET, 0=no action, 1=reset ADC
* bit 13-12     10:     SOFT and FREE, 10=stop after current conversion
* bit 11-8      0000:   ACQ_Prescaler, 0000 = 1 x Tclk
* bit 7         0:      CPS, 0: Fclk=CPUCLK/1, 1: Fclk=CPUCLK/2
* bit 6         0:      CONT_RUN, 0=start/stop mode, 1=continuous run
* bit 5         0:      0=hi priority int, 1=low priority int
* bit 4         1:      0=dual sequencer, 1=cascaded sequencer
* bit 3         0:      0=calibration mode disabled
* bit 2         0:      BRG_ENA, used in calibration mode only
* bit 1         0:      HI/LO, no effect in normal operation mode
* bit 0         0:      0=self-test mode disabled

        SPLK    #0100011100000010b, ADCTRL2
*                ||||||||||||||||
*                FEDCBA9876543210
* bit 15        0:      EVB_SOC_SEQ, 0=no action
* bit 14        0:      RST_SEQ1/STRT_CAL, 0=no action
* bit 13        0:      SOC_SEQ1, 0=clear any pending SOCs
* bit 12        0:      SEQ1_BSY, read-only
* bit 11-10     01:     INT_ENA_SEQ1, 01=int on every SEQ1 conv
* bit 9         1:      INT_FLAG_SEQ1, write 1 to clear
* bit 8         1:      EVA_SOC_SEQ1, 1=SEQ1 start from EVA
* bit 7         0:      EXT_SOC_SEQ1, 1=SEQ1 start from ADCSOC pin
* bit 6         0:      RST_SEQ2, 0=no action
* bit 5         0:      SOC_SEQ2, no effect in cascaded mode
* bit 4         0:      SEQ2_BSY, read-only
* bit 3-2       00:     INT_ENA_SEQ2, 00=int disabled
* bit 1         1:      INT_FLAG_SEQ2, write 1 to clear
* bit 0         0:      EVB_SOC_SEQ2, 1=SEQ2 started by EVB

;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Setup the buffer for the ADC results
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
        LDP     #adc_buf_ptr      ;set data page
        LAR     AR0, #adc_buf     ;pointer to results buffer
        SAR     AR0, adc_buf_ptr  ;initialize adc_buf_ptr
        MAR     *, AR0            ;ARP = AR0
        LACC    #2407h            ;ACC=0x2407
        LDP     #temp
        SPLK    #adc_buf_len-1, temp
        RPT     temp              ;repeat #adc_buf_len-1 times
        SACL    *+                ;initialize the buffer

;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Setup GP Timer2 to trigger an ADC conversion
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
        LDP     #DP_EVA           ;set data page

        SPLK    #0000h, T2CNT     ;clear timer2 counter
        SPLK    #adc_rate, T2PR   ;set timer2 period

        SPLK    #0000010000000000b, GPTCONA  ;init GPTCON register
*                ||||||||||||||||
*                FEDCBA9876543210
* bit 15        0:      reserved
* bit 14        0:      T2STAT - read only
* bit 13        0:      T1STAT - read only
* bit 12-11     00:     reserved
* bit 10-9      10:     T2TOADC, 10 = ADCSOC on period match
* bit 8-7       00:     T1TOADC, 00 = no ADCSOC
* bit 6         0:      1 = enable all timer compare outputs
* bit 5-4       00:     reserved
* bit 3-2       00:     00 = T2PIN forced low
* bit 1-0       00:     00 = T1PIN forced low

        SPLK    #0001000001000000b, T2CON   ;init T2CON register
*                ||||||||||||||||
*                FEDCBA9876543210
* bit 15-14     00:     stop immediately on emulator suspend
* bit 13        0:      reserved
* bit 12-11     10:     10 = continous-up count mode
* bit 10-8      000:    000 = x/1 prescaler
* bit 7         0:      0 = use own TENABLE bit
* bit 6         1:      1 = enable timer
* bit 5-4       00:     00 = CPUCLK is clock source
* bit 3-2       00:     00 = reload compare reg on underflow
* bit 1         0:      0 = disable timer compare
* bit 0         0:      0 = use own period register

;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Setup the event manager interrupts
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
        LDP     #DP_EVA          ;set data page
        SPLK    #0FFFFh, EVAIFRA ;clear all EVA group A interrupts
        SPLK    #0FFFFh, EVAIFRB ;clear all EVA group B interrupts
        SPLK    #0FFFFh, EVAIFRC ;clear all EVA group C interrupts
        SPLK    #00000h, EVAIMRA ;enabled desired EVA group A interrupts
        SPLK    #00000h, EVAIMRB ;enabled desired EVA group B interrupts
        SPLK    #00000h, EVAIMRC ;enabled desired EVA group C interrupts

        LDP     #DP_EVB          ;set data page
        SPLK    #0FFFFh, EVBIFRA ;clear all EVB group A interrupts
        SPLK    #0FFFFh, EVBIFRB ;clear all EVB group B interrupts
        SPLK    #0FFFFh, EVBIFRC ;clear all EVB group C interrupts
        SPLK    #00000h, EVBIMRA ;enabled desired EVB group A interrupts
        SPLK    #00000h, EVBIMRB ;enabled desired EVB group B interrupts
        SPLK    #00000h, EVBIMRC ;enabled desired EVB group C interrupts

;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Enable global interrupts
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
        CLRC    INTM            ;enable global interrupts

;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Main loop
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
loop:   NOP
        B       loop            ;branch to loop



**********************************************************************
*  G E N E R A L  I N T E R R U P T  S E R V I C E  R O U T I N E S  *
**********************************************************************

;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;ADC Interrupt Service Routine
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
adc_isr:

;context save
        MAR     *,AR1              ;ARP=stack pointer
        MAR     *+                 ;skip one stack location
        SST     #1, *+             ;save ST1
        SST     #0, *+             ;save ST0
        SACH    *+                 ;save ACCH
        SACL    *+                 ;save ACCL
        SAR     AR2, *+            ;save AR2

;clear the INT_FLAG_SEQ1 and read the ADC result
        CLRC    SXM
        LDP     #DP_PF2             ;set data page
        LACC    ADCTRL2             ;read and write ADCTRL2
        SACL    ADCTRL2             ;  to clear the INT_FLAG_SEQ1
        LACC    RESULT0,10          ;read ADC RESULT0

;store the data value to the buffer
        LDP     #adc_buf_ptr        ;set data page
        LAR     AR2, adc_buf_ptr    ;AR2 points to the buffer
        MAR     *, AR2              ;set ARP
        SACH    *+                  ;store result
        SAR     AR2, adc_buf_ptr    ;store updated pointer

;brute-force the circular buffer
        LAR     AR0, #(adc_buf+adc_buf_len-1)  ;AR0 points to last buffer entry
        CMPR    2                              ;TC set if AR(ARP) > AR0
        BCND    adc_isr1, NTC                  ;branch if TC not set
        SPLK    #adc_buf, adc_buf_ptr          ;re-init the pointer

adc_isr1:

;reset ADC SEQ1 to CONV00 state
        LDP     #DP_PF2             ;set data page
        LACC    ADCTRL2             ;read ADCTRL2
        OR      #4000h              ;set bit 14 (RST_SEQ1/STRT_CAL bit)
        SACL    ADCTRL2             ;write back to reset SEQ1 

;toggle the IOPA2 pin
        LDP     #DP_PF2             ;set data page
        LACC    PADATDIR            ;ACC = PADATDIR
        XOR     #0004h              ;toggle IOPA2 bit
        SACL    PADATDIR            ;write back to GPIO port register

;context restore
        MAR     *, AR1              ;ARP = AR1
        MAR     *-                  ;SP points to last entry
        LAR     AR2, *-             ;restore AR2
        LACL    *-                  ;restore ACCL
        ADD     *-,16               ;restore ACCH
        LST     #0, *-              ;restore ST0
        LST     #1, *-              ;restore ST1, de-allocate skipped stack location
        CLRC    INTM                ;re-enable global interrupts
        RET