📄 ad.asm
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; SOLUTION FILE FOR LAB11.ASM
.global start
.def adc_isr
.include f2407.h ;address definitions
adc_rate .set 599 ;50KHz sampling rate
adc_buf_len .set 300 ;ADC results buffer length
stk_len .set 100 ;stack length
.bss temp,1 ;general purpose variable
adc_buf_ptr .usect "buffer",1 ;ptr to next free buff addr
adc_buf .usect "buffer",adc_buf_len ;reserve space for buffer
stk .usect "stack",stk_len ;reserve space for stack
.text
start:
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Disable the watchdog
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
LDP #DP_PF1 ;set data page
SPLK #11101000b, WDCR
* bit 7 1: clear WD flag
* bit 6 1: disable the dog
* bit 5-3 101: must be written as 101
* bit 2-0 000: WDCLK divider = 1
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Setup the system control registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
LDP #DP_PF1 ;set data page
SPLK #0000000011111101b, SCSR1
; ||||||||||||||||
; FEDCBA9876543210
* bit 15 0: reserved
* bit 14 0: CLKOUT = CPUCLK
* bit 13-12 00: IDLE1 selected for low-power mode
* bit 11-9 000: PLL x4 mode
* bit 8 0: reserved
* bit 7 1: 1 = enable ADC module clock
* bit 6 1: 1 = enable SCI module clock
* bit 5 1: 1 = enable SPI module clock
* bit 4 1: 1 = enable CAN module clock
* bit 3 1: 1 = enable EVB module clock
* bit 2 1: 1 = enable EVA module clock
* bit 1 0: reserved
* bit 0 1: clear the ILLADR bit
SPLK #0000000000001111b, SCSR2
; ||||||||||||||||
; FEDCBA9876543210
* bit 15-6 0's: reserved
* bit 5 0: DO NOT clear the WD OVERRIDE bit
* bit 4 0: XMIF_HI-Z, 0=normal mode, 1=Hi-Z'd
* bit 3 1: 1 = disable the BOOT ROM
* bit 2 1: MP/MC*, 1 = Flash addresses mapped external
* bit 1-0 11: 11 = SARAM mapped to prog and data
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Set wait states for external memory interface on LF2407 EVM
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
LDP #temp ;set data page
SPLK #0000000001000000b, temp
; ||||||||||||||||
; FEDCBA9876543210
* bit 15-11 0's: reserved
* bit 10-9 00: bus visibility off
* bit 8-6 001: 1 wait-state for I/O space
* bit 5-3 000: 0 wait-state for data space
* bit 2-0 000: 0 wait-state for program space
OUT temp, WSGR
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Setup the software stack
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
LAR AR1, #stk ;AR1 is stack pointer
MAR *, AR1 ;ARP = AR1
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Setup the core interrupts
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
LDP #0h ;set data page
SPLK #111111b,IFR ;clear any pending interrupts
SPLK #000001b,IMR ;enable desired interrupts
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Setup shared I/O pins
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
LDP #DP_PF2 ;set data page
SPLK #0000000000000000b,MCRA
* ||||||||||||||||
* FEDCBA9876543210
* bit 15 0: 0=IOPB7, 1=TCLKINA
* bit 14 0: 0=IOPB6, 1=TDIRA
* bit 13 0: 0=IOPB5, 1=T2PWM/T2CMP
* bit 12 0: 0=IOPB4, 1=T1PWM/T1CMP
* bit 11 0: 0=IOPB3, 1=PWM6
* bit 10 0: 0=IOPB2, 1=PWM5
* bit 9 0: 0=IOPB1, 1=PWM4
* bit 8 0: 0=IOPB0, 1=PWM3
* bit 7 0: 0=IOPA7, 1=PWM2
* bit 6 0: 0=IOPA6, 1=PWM1
* bit 5 0: 0=IOPA5, 1=CAP3
* bit 4 0: 0=IOPA4, 1=CAP2/QEP2
* bit 3 0: 0=IOPA3, 1=CAP1/QEP1
* bit 2 0: 0=IOPA2, 1=XINT1
* bit 1 0: 0=IOPA1, 1=SCIRXD
* bit 0 0: 0=IOPA0, 1=SCITXD
SPLK #1111111000000000b,MCRB
* ||||||||||||||||
* FEDCBA9876543210
* bit 15 1: 0=reserved, 1=TMS2 (always write as 1)
* bit 14 1: 0=reserved, 1=TMS (always write as 1)
* bit 13 1: 0=reserved, 1=TD0 (always write as 1)
* bit 12 1: 0=reserved, 1=TDI (always write as 1)
* bit 11 1: 0=reserved, 1=TCK (always write as 1)
* bit 10 1: 0=reserved, 1=EMU1 (always write as 1)
* bit 9 1: 0=reserved, 1=EMU0 (always write as 1)
* bit 8 0: 0=IOPD0, 1=XINT2/ADCSOC
* bit 7 0: 0=IOPC7, 1=CANRX
* bit 6 0: 0=IOPC6, 1=CANTX
* bit 5 0: 0=IOPC5, 1=SPISTE
* bit 4 0: 0=IOPC4, 1=SPICLK
* bit 3 0: 0=IOPC3, 1=SPISOMI
* bit 2 0: 0=IOPC2, 1=SPISIMO
* bit 1 0: 0=IOPC1, 1=BIO*
* bit 0 0: 0=IOPC0, 1=W/R*
SPLK #0000000000000000b,MCRC
* ||||||||||||||||
* FEDCBA9876543210
* bit 15 0: reserved
* bit 14 0: 0=IOPF6, 1=IOPF6
* bit 13 0: 0=IOPF5, 1=TCLKINB
* bit 12 0: 0=IOPF4, 1=TDIRB
* bit 11 0: 0=IOPF3, 1=T4PWM/T4CMP
* bit 10 0: 0=IOPF2, 1=T3PWM/T3CMP
* bit 9 0: 0=IOPF1, 1=CAP6
* bit 8 0: 0=IOPF0, 1=CAP5/QEP4
* bit 7 0: 0=IOPE7, 1=CAP4/QEP3
* bit 6 0: 0=IOPE6, 1=PWM12
* bit 5 0: 0=IOPE5, 1=PWM11
* bit 4 0: 0=IOPE4, 1=PWM10
* bit 3 0: 0=IOPE3, 1=PWM9
* bit 2 0: 0=IOPE2, 1=PWM8
* bit 1 0: 0=IOPE1, 1=PWM7
* bit 0 0: 0=IOPE0, 1=CLKOUT
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Setup IOPA2 pin for use as output
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
LDP #DP_PF2 ;set data page
LACC PADATDIR ;ACC = PADATDIR
OR #0400h ;IOPA2 is output
SACL PADATDIR ;write back to GPIO port register
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Setup the ADC
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
LDP #DP_PF2 ;set data page
SPLK #0100000000000000b, ADCTRL1
* ||||||||||||||||
* FEDCBA9876543210
* bit 14 1: 1 = reset ADC module
SPLK #0000000000000000b, MAX_CONV
* ||||||||||||||||
* FEDCBA9876543210
* bit 15-7 0's: reserved
* bit 6-4 000: MAX_CONV2 value
* bit 3-0 0000: MAX_CONV1 value (0 means 1 conversion)
SPLK #0000000000000000b, CHSELSEQ1
* ||||||||||||||||
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