arbi_pulsegen.vhd

利用fpga实现的任意脉冲波形产生器 很有用的vhd代码

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:40:24 11/26/2008 
-- Design Name: 
-- Module Name:    Arbi_PulseGen - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Arbi_PulseGen is
	 GENERIC(CNT_WIDTH: integer:=20);
    Port ( RESET : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           PRI : in  STD_LOGIC_VECTOR(CNT_WIDTH-1 downto 0);
           PW : in  STD_LOGIC_VECTOR(CNT_WIDTH-1 downto 0);
           PULSE : out  STD_LOGIC);
end Arbi_PulseGen;

architecture Behavioral of Arbi_PulseGen is
	signal gen_cnt: std_logic_vector(CNT_WIDTH-1 downto 0):=(others=>'0');
	signal pulse_ind: std_logic:='0';
begin
	--
	CNT_PROCESS:process(CLK,RESET)
	begin
		if rising_edge(CLK) then
			if RESET='1' then
				gen_cnt<=(others=>'0');
			else
				if gen_cnt>=PRI then
					gen_cnt<=(others=>'0');
				else
					gen_cnt<=gen_cnt+'1';
				end if;
			end if;
		end if;
	end process CNT_PROCESS;
	--
	PULSE_GEN:process(CLK,RESET)
	begin
		if rising_edge(CLK) then
			if RESET='1' then
				pulse_ind<='0';
			else
				if gen_cnt>0 and gen_cnt<=PW then
					pulse_ind<='1';
				else
					pulse_ind<='0';
				end if;
			end if;
		end if;
	end process PULSE_GEN;
	--
	PULSE_REG_OUT:process(CLK)
	begin
		if rising_edge(CLK) then
			PULSE<=pulse_ind;
		end if;
	end process;
end Behavioral;