4抽头直接fir滤波器vhdl设计.txt

好不容易找的四抽头的滤波器设计！！需要的请

4抽头直接FIR滤波器VHDL设计
系数为{-1，3.75，3.75，-1}的滤波器的VHDL设计代码经本人综合仿真 如下：
以下内容需要回复才能看到
package eight_bit_int is --user defined types
subtype byte is integer range -128 to 127;
type array_byte is array(0 to 3)of byte;
end eight_bit_int;
library work;
use work.eight_bit_int.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity fir_srg is   ----->interface
port (clk : in  std_logic;
  x : in  byte;
  y : out byte);
end fir_srg;
architecture flex of fir_srg is
signal tap :array_byte; --tapped delay line of bytes
begin 
p1:process   ----->behavioral style
begin 
wait until clk='1';
--compute output y with the filter coefficients weight.
--the coefficients are [-1 3.75 3.75 -1].
--multiplication and division for altera vhdl are only
--allowed for powers of two!
y<=2*tap(1)+tap(1)+tap(1)/2+tap(1)/4
   +2*tap(2)+tap(2)+tap(2)/2+tap(2)/4
   -tap(3)-tap(0);
for i in 3 downto 1 loop
tap(i)<=tap(i-1);--tapped delay line:shift one
end loop;
tap(0)<=x;
end process;
end flex;