cpu_support.s

epson usb2.0 控制芯片 S1R72V05 固件程序。

/*
 *  The above copyright holder, limited to cases in which one satisfies 
 *  conditions (1) ~ (4) below, or the conditions described in Version 2 
 *  of of the GNU Public License officially announced by the Free Software 
 *  Foundation, consents to the use, reproduction, alteration, and 
 *  redistribution (hereafter called utilization) of this software (this 
 *  software includes alterations, likewise below) without compensation. 
 *
 *  (1) When this software is utilized in the form of source code, the 
 *  above copyright declaration, these conditions of utilization, and the 
 *  following stipulation of no guarantee shall be included in unchanged 
 *  form inside the source code.
 *  (2) When this software is redistributed in a form in which it can be 
 *  used in the development of other software, library form, etc., the above
 *  copyright display, these terms of utilization, and the following 
 *  stipulation of no guarantee shall be inserted in documentation accompanying
 *  redistribution (user's manual, etc.).
 *  (3) When this software is redistributed in a form in which it cannot be used
 *  in the development of other software, embedded in devices, etc., one of the 
 *  following conditions shall be satisfied.
 *		(a) The above copyright display, these terms of utilization, and the 
 *		following stipulation of no guarantee shall be inserted in documentation 
 *		accompanying redistribution (user's manual, etc.). 
 *		(b) The TOPPERS Project shall be notified owing to a method in which the 
 *		form of distribution is decided otherwise. 
 *		(4) The above copyright holder and the TOPPERS Project shall be exempt 
 *		from responsibility for whatever damages occur either directly or indirectly
 *		through the utilization of this software.
 *
 *	This software is something that is provided with no guarantee. The above copyright
 *  holder and the TOPPERS Project make no guarantee whatsoever in regard to this 
 *  software, including the possibility of its application. In addition, the above 
 *  copyright holder and the TOPPERS Project shall also not bear responsibility for
 *  whatever damages occur either directly or indirectly through the utilization of
 *  this software.
 *
 *  @(#) $Id: cpu_support.S,v 1.3 2006/08/10 08:11:37 0684248 Exp $
 */

/*
 * Processor dependence module assembly language part(for ARMv4)
 */
#define _MACRO_ONLY
#include "jsp_kernel.h"
#include "offset.h"
#include <armv4.h>
#include <t_config.h>
        
/*
 *  Task dispatcher
 *
 *  It is necessary to call dispatch with the system mode and the interruption prohibited.
 *  Because exit_and_dispatch also has the principle of call in system mode and interruption prohibited,
 *  in order to corespond to the kernel stat-up ,it also corresponds to the case of calling it in the IRQ mode.
 */

        .text
        .align 4    
        .globl dispatch
        .globl exit_and_dispatch
dispatch:
        stmfd sp!, {r4 - r11,lr}   /* Save the register */
        ldr   r0, =runtsk          /* Read the runtsk */
        ldr   r1, [r0]
        str   sp, [r1,#TCB_sp]      /* Save the task stack */
        adr   r2, dispatch_r
        str   r2, [r1,#TCB_pc]      /* Save the execution restart address number.   */
        ldr   r6, =interrupt_count  /* r6 <-interrupt_count */
        mov   r5, #(CPSR_SVC|CPSR_IRQ_BIT)  /* Disable the interrupt(system mode)  */
        mov   r4, #(CPSR_SVC)               /* Enable the interrupt(system mode) */
        b     dispatcher_1

dispatch_r:
        ldmfd sp!,{r4 - r11,lr}
        /*
 		 * Start the routine of task exception process
         * Because dispatch_r is called from dispatcher_1
		 * The address of tcb is in r1. 
         */
        ldr   r0,[r1,#TCB_enatex]
        tst   r0,#TCB_enatex_mask
        beq   dispatch_r_1          /* If enatex is FALSE, return. */
        ldr   r0,[r1,#TCB_texptn]   /* Load texptn 				*/
        tst   r0,r0                 /* If texptn is 0 			*/
        bne   call_texrtn           /* Call the task exception routine */
dispatch_r_1:   
        mov   pc,lr        



exit_and_dispatch:
        ldr   r6, =interrupt_count /* clear interrupt_count to 0 */
        mov   r3, #0        
        str   r3, [r6]                                        
        /*
		 * FIQ is always prohibited. 
         */
        mov   r5, #(CPSR_SVC|CPSR_IRQ_BIT) /* Disable the interrupt(System mode) */
        mov   r4, #(CPSR_SVC)              /* Enable the interrupt(system mode) */
        mrs   r0, cpsr                     /* Inherit FIQ  */
        and   r0, r0, #CPSR_FIQ_BIT
        orr   r0, r0, r5
        msr   cpsr, r0          /* System mode  */
dispatcher_1:
        /*
		 *  The system mode and interrupt should be prohibited here. 
         */
        ldr   r0, =schedtsk   /* Read schedtsk */
        ldr   r1, [r0]
        ldr   r2, =runtsk     /* schedtsk to runtsk */
        str   r1, [r2]        /* Runtsk to NULL when there is no schedtsk  */
        cmp   r1, #0
        beq   dispatcher_2        
dispatcher_3:           
        ldr   sp, [r1,#TCB_sp] /* Return the task stack */
        ldr   pc, [r1,#TCB_pc] /* Return the actual execution address */
dispatcher_2:
        mov   r3,#1
        str   r3, [r6]         /* interupt_count = 1 */
        ldr   sp, =STACKTOP
        /* If the CPU is hold in the sleep mode, rewrites it.  */
        mrs   r0, cpsr        /* Inherit FIQ  */
        and   r0, r0, #CPSR_FIQ_BIT
        orr   r0, r0, r4
        msr   cpsr, r0        /* Waiting for interrupt */
        WAIT_INTERRUPT
        mrs   r0, cpsr        /* Inherit FIQ  */
        and   r0, r0, #CPSR_FIQ_BIT
        orr   r0, r0, r5
        msr   cpsr, r0        /* Disable the interrupt */
        mov   r3,#0
        str   r3, [r6]        /* interrupt_count = 0 */   
        b     dispatcher_1


                
/*
 * Processing when task starts
 */
        .text
        .globl activate_r
activate_r:
        mov   r1,#(CPSR_SVC|CPSR_FIQ_BIT) /* Enable the interrupt(system mode) */
        mrs   r2, cpsr         /* Inherit FIQ  */
        and   r2, r2, #CPSR_FIQ_BIT
        orr   r1, r1, r2            
        msr   cpsr, r1         /* Enable the interrupt */
        ldr   lr, =ext_tsk     /* Set the return address */
        ldmfd sp!, {r0,pc}     /* Set parameter,PC */


        
/*
 *  Interruption handler/CPU exception handler exit processing
 *
 *  ret_int is called in system mode and IRQ interrupt disbale state .
 *
 */
        .text
        .globl ret_int
        .globl ret_exc 
ret_int:
ret_exc:                
        /*
 		 * Come in the system mode. 
         */
        ldr   r2, =runtsk       /* Read runtsk */
        ldr   r1, [r2]
        ldr   r2, =enadsp
        ldr   r0, [r2]
        cmp   r0, #0
        beq   ret_int_1
        ldr   r2, =schedtsk
        ldr   r0, [r2]
        cmp   r0, r1            /* Compare the schedtsk and runtsk */
        beq   ret_int_1
        stmfd sp!, {r4-r11}     /* Save the remainder register  */
        str   sp, [r1,#TCB_sp]  /* Push to the task stack */
        adr   r0, ret_int_r     /* Pusb the actual execution address */
        str   r0, [r1,#TCB_pc]
        b     dispatcher_1
ret_int_r:
        ldmfd sp!, {r4-r11}     /* Pop return the register */
ret_int_1:
        /*
 		 * Start the task exception routine
         * Because dispatch_r is called from dispatcher_1
		 * The address of tcb is in r1. 
         * ret_int_1 is called from ret_exe
         */
        ldr   r0, [r1,#TCB_enatex]
        tst   r0, #TCB_enatex_mask
        beq   ret_int_2              /* If enatex is FALSE,return */
        ldr   r0, [r1,#TCB_texptn]   /* Load texptn 			 */
        tst   r0, r0                 /* If texptn is 0 			 */
        blne  call_texrtn            /* Call the task exception routine */
ret_int_2:              
        ldmfd sp!, {r0}       /* Return the spsr */
        mrs   r2, cpsr        /* Inherit FIQ  */
        and   r2, r2, #CPSR_FIQ_BIT
        and   r0, r0, #~CPSR_FIQ_BIT
        orr   r0, r0, r2                    
        msr   cpsr, r0      
        ldmfd sp!, {r0 - r3,ip,lr,pc} /* Return the task */
        
        /*
 		 * wait for a while
         */
	.globl sil_dly_nse
sil_dly_nse:
        sub   r0, r0, #SIL_DLY_TIM1
        cmp   r0, #0
        bgt   _sil_dly_nse1
        movle pc, lr
_sil_dly_nse1:
        sub   r0, r0, #SIL_DLY_TIM2
        cmp   r0, #0
        bgt   _sil_dly_nse1
        movle pc, lr