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/*
* The above copyright holder, limited to cases in which one satisfies
* conditions (1) ~ (4) below, or the conditions described in Version 2
* of of the GNU Public License officially announced by the Free Software
* Foundation, consents to the use, reproduction, alteration, and
* redistribution (hereafter called utilization) of this software (this
* software includes alterations, likewise below) without compensation.
*
* (1) When this software is utilized in the form of source code, the
* above copyright declaration, these conditions of utilization, and the
* following stipulation of no guarantee shall be included in unchanged
* form inside the source code.
* (2) When this software is redistributed in a form in which it can be
* used in the development of other software, library form, etc., the above
* copyright display, these terms of utilization, and the following
* stipulation of no guarantee shall be inserted in documentation accompanying
* redistribution (user's manual, etc.).
* (3) When this software is redistributed in a form in which it cannot be used
* in the development of other software, embedded in devices, etc., one of the
* following conditions shall be satisfied.
* (a) The above copyright display, these terms of utilization, and the
* following stipulation of no guarantee shall be inserted in documentation
* accompanying redistribution (user's manual, etc.).
* (b) The TOPPERS Project shall be notified owing to a method in which the
* form of distribution is decided otherwise.
* (4) The above copyright holder and the TOPPERS Project shall be exempt
* from responsibility for whatever damages occur either directly or indirectly
* through the utilization of this software.
*
* This software is something that is provided with no guarantee. The above copyright
* holder and the TOPPERS Project make no guarantee whatsoever in regard to this
* software, including the possibility of its application. In addition, the above
* copyright holder and the TOPPERS Project shall also not bear responsibility for
* whatever damages occur either directly or indirectly through the utilization of
* this software.
*
* @(#) $Id: sys_support.S,v 1.4 2006/08/10 08:11:38 0684248 Exp $
*/
#define _MACRO_ONLY
#include "jsp_kernel.h"
#include <toya2.h>
/*
* low-level initialization of dependence for target system
*
* It is called in a start-up module before initialization of the memory.
*/
.section .init
.align 4
.global hardware_init_hook
hardware_init_hook:
//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
//; Set AHB-Lite IP(AIPI is set in the BROM of BOOT)
//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ldr r1,=0x10000000
ldr r3,=0x00040304
str r3,[r1]
ldr r1,=0x10020000
ldr r3,=0x00000000
str r3,[r1]
ldr r1,=0x10000004
ldr r3,=0xFFFBFCFB
str r3,[r1]
ldr r1,=0x10020004
ldr r3,=0xFFFFFFFF
str r3,[r1]
ldr r1,=0x10000008
ldr r3,=0x00000001
str r3,[r1]
ldr r1,=0x10020008
str r3,[r1]
//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
//; Set CS0/1
//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
//;comment # CS0 Initialization (Async Mode)
//;comment # 32-bit, ?? wait states
//;setmem 0xDF001000 0x00000900 32
//;setmem 0xDF001004 0x00000E01 32
ldr r1,=0xDF001000
//; ldr r3,=0x00000900
ldr r3,=0x00000901
str r3,[r1]
ldr r1,=0xDF001004
ldr r3,=0x00000E01
str r3,[r1]
//;comment # Setting for Memory Map IO Port
//;comment # CS1 Initialization (Async Mode)
//;comment # 16-bit, D0..15, ?? wait states
//;setmem 0xDF001008 0x02022000 32
//;setmem 0xDF00100C 0x11112501 32
ldr r1,=0xDF001008
//;ES1
#if CS1_NON_BURST
ldr r3,=0x04040533
#else
ldr r3,=0x00110503 // For burst
#endif
//;FPGA
//; ldr r3,=0x04140733
str r3,[r1]
ldr r1,=0xDF00100c
#if CS1_NON_BURST
ldr r3,=0x11112511
#else
ldr r3,=0x11111511 // For burst
#endif
str r3,[r1]
//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
//; Set PLL
//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
//;{Changed for TO2
//;# Explicitly set MPLL 266MHz
//;comment setmem 0x10027004 0x007b1C73 32
//; ldr r1,=0x10027004
//; ldr r3,=0x007b1C73
//; str r3,[r1]
//;# Explicitly set MPLL 288MHz
ldr r1,=0x10027004
ldr r3,=0x0272216D
str r3,[r1]
//;comment comment # PLL 66MHz
//;comment setmem 0x10027000 0x77000207 32
//;
//; ldr r1,=0x10027000
//; ldr r3,=0x77000207
//; str r3,[r1]
//;comment comment # PLL 88.67MHz
//;setmem 0x10027000 0x17000a07 32
ldr r1,=0x10027000
#if PLL88MHZ
ldr r3,=0x17000a07
#elif PLL48MHZ
//;comment comment # PLL 48.00MHz
ldr r3,=0x17001207
#endif
str r3,[r1]
//;comment # PLL 133MHz
//;comment setmem 0x10027000 0x17000607 32
//; ldr r1,=0x10027000
//; ldr r3,=0x17000607
//; str r3,[r1]
//; TO2 }
//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
//; Set SDRAM controller
//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
//;comment # FMCR Register
//;comment # Select CS3 and CSD0
//;setmem 0x10027814 0xFFFFFFC9 32
ldr r1,=0x10027814
ldr r3,=0xFFFFFFC9
str r3,[r1]
//;comment Set Precharge Command
//;setmem 0xDF000000 0x92120300 32
ldr r1,=0xDF000000
ldr r3,=0x92120300
str r3,[r1]
//;comment Issue Precharge all Command
//;memory 0xC0200000 +1 32
LDR r3, =0xC0200000
LDR r2, [r3]
//;comment Set AutoRefresh Command
//;setmem 0xDF000000 0xA2120300 32
LDR r3, =0xA2120300
STR r3, [r1]
//; Issue AutoRefresh Command
LDR r3, =0xC0000000
LDR r2, [r3]
LDR r2, [r3]
LDR r2, [r3]
LDR r2, [r3]
LDR r2, [r3]
LDR r2, [r3]
LDR r2, [r3]
LDR r2, [r3]
//;comment Set Mode Register
//;setmem 0xDF000000 0xB2120300 32
LDR r3, =0xB2120300
STR r3, [r1]
//;comment Issue Mode Register Command
//;comment Burst Length = 8
//;memory 0xC0119800 +1 32
LDR r3, =0xC0119800 //;; Mode Register Value
LDR r2, [r3]
//;comment Set to Normal Mode
//;comment # From the spec of the SDRAM K4S56163LC-RG75000,
//;comment # 1. tRCD = 19ns minimum -> RCD = 3 clk (SDCLK=133MHz) -> SRCD = 11b
//;comment # 2. tRP = 19ns minimum -> RP = 3 clk (SDCLK=133MHz) -> SRP = 0b
//;comment # 3. tRC = 65ns minimum -> RC = 9 clk (SDCLK=133MHz) -> SRC = 1001b
//;comment # 4. refresh rate = 8192rows/64ms -> SREFR = 11b
//;setmem 0xDF000000 0x8212F339 32
LDR r3, =0x8212F339
STR r3, [r1]
// The TOYA2 exception vector is configured to High Memory (since 0xFFFFFF00).
//; Copy Interrupt Vector to High Memory
LDR r0, =0xFFFFFEF0
LDR r1, =VECTOR_COPY_START
LDR r2, =VECTOR_COPY_END
VectorCopy:
LDR r3, [r1]
STR r3, [r0]
ADD r0, r0, #0x4
ADD r1, r1, #0x4
CMP r1, r2
BNE VectorCopy
b _MMU_init // Initialize MMU
VECTOR_COPY_START:
.long undef_exception
.long swi_exception
.long prefetch_exception
.long data_abort_exception
.long IRQ_Handler
.long fiq_exception
VECTOR_COPY_END:
//-------------------------------------------------------------------------------
// Memory Management Unit Configuration and Cache control Program
//-------------------------------------------------------------------------------
CPUID_CODE = 0x29200 // Device ID code.
CACHE_LNG = 0x20 // Cache Line length = 32 bytes.
R1_SBZ_DATA = 0xFFFA0C00 // SBZ data for MMU control register.
R1_SBO_DATA = 0x00050078 // SBO data for MMU control register.
D_DOMAIN_ACCESS = 0x55555555 // Domain access permission word
MVA_SBZ = 0x0000001F // SBZ data for MVA format line.
INDEX_SBZ = 0x03FFFF1F // SBZ data for Index format line.
TTBSZ_SEC = 0x00100000 // 1024KB size
TTBSZ_COARSE = 0x00010000 // 64KB size
TTBSZ_SMALL = 0x00001000 // 4KB size
TTBMSK_SEC = 0xFFF00000 // Bit Mask for 1MB page address.
TTBMSK_COARSE = 0xFFFFFC00 // Bit Mask for Coarse page address.
TTBMSK_SMALL = 0xFFFFF000 // Bit Mask for 4KB page address.
TTB_FAULT = 0x00 // Fault entry.
TTB_COARSE = 0x11 // Coarse base table entry(4KB or 64KB page)
TTB_SECTION = 0x12 // Section base table entry(1MB page)
TTB_FINE = 0x13 // Fine table entry (1KB page)
ATR_WB = 0x0C // Buffered Cache control (Write Back)
ATR_WT = 0x08 // Cache without buffer (Write Through)
AP_RO = 0x0800 // Read Only type access for User mode
AP_RW = 0x0C00 // Read/Write type access for User mode.
AP_MSK = 0x0C00 // Mask bits for Aceess Permission control.
ATR_MSK = 0x0C // Mask bits for Attribute control.
DOMAIN_MSK = 0x01E0 // Mask bits for Domain control.
//-------------------------------------------------------------------------------
// Definitions for Level-2 Descriptor.
TTBL2_LARGE = 0x01 // Large 64KB page entry.
TTBL2_SMALL = 0x02 // Small 4KB page entry.
TTBL2_TINY = 0x03 // Tiny 1KB page entry.
// TTB base address must be aligned to 16KB boundery.
TTB_ADDR = 0xC3F00000 // TTB base address.
TTB_SIZE = 0x1000 // 4096 maximum entries.
CTTB_ADDR = 0xC3F04000 // Coarse TTB base address.
CTTB_SIZE = 0x100 // 256 Maximum entries. (4KB page)
FTTB_SIZE = 0x400 // 1024 Maximum entries (1KB page) for Fine table
//-------------------------------------------------------------------------------
BROM_LADDR = 0x00000000 // Logical address for Bootstrap ROM
BROM_PADDR = 0x00000000
BROM_SIZE = 0x00100000 // Size = 1MB.
BROM_ATR = AP_RO+ATR_WT
SFR_LADDR = 0x10000000 // Logical address for Internal Register area
SFR_PADDR = 0x10000000 // Physical address for Internal Register area
SFR_SIZE = 0x00044000 // Size = 272KB.
SFR_ATR = AP_RW
SDRAM_LADDR = 0xC0000000 // Logical address for SDRAM
SDRAM_PADDR = 0xC0000000 // Physical address for SDRAM
SDRAM_SIZE = 0x04000000 // Size = 64MB.
SDRAM_ATR = AP_RW+ATR_WB
FLASH_LADDR = 0xC8000000 // Logical address for FLASH ROM (CS0 Bank)
FLASH_PADDR = 0xC8000000 // Physical address for FLASH ROM (CS0 Bank)
FLASH_SIZE = 0x02000000 // Size = 32MB.
FLASH_ATR = AP_RW+ATR_WT
EXT_LADDR = 0xCC000000 // Logical address for External Register (CS1 Bank)
EXT_PADDR = 0xCC000000 // Physical address for External Register (CS1 Bank)
EXT_SIZE = 0x01000000 // Size = 16MB.
EXT_ATR = AP_RW
CSI_LADDR = 0x80000000 // Logical address for CSI Bank
CSI_PADDR = 0x80000000 // Physical address for CSI Bank
CSI_SIZE = 0x00001000 // Size = 4KB.
CSI_ATR = AP_RW
BMI_LADDR = 0xA0000000 // Logical address for BMI Bank
BMI_PADDR = 0xA0000000 // Physical address for BMI Bank
BMI_SIZE = 0x00001000 // Size = 4KB.
BMI_ATR = AP_RW
CF_LADDR = 0xD4000000 // Logical address for Internal Register area
CF_PADDR = 0xD4000000 // Physical address for Internal Register area
CF_SIZE = 0x04000000 // Size = 64MB.
CF_ATR = AP_RW
EMI_LADDR = 0xDF000000 // Logical address for Internal Register area
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