sys_config.c

epson usb2.0 控制芯片 S1R72V05 固件程序。

/*
 *	The above copyright holder, limited to cases in which one satisfies
 *	conditions (1) ~ (4) below, or the conditions described in Version 2
 *	of of the GNU Public License officially announced by the Free Software
 *	Foundation, consents to the use, reproduction, alteration, and
 *	redistribution (hereafter called utilization) of this software (this
 *	software includes alterations, likewise below) without compensation.
 *
 *	(1) When this software is utilized in the form of source code, the
 *	above copyright declaration, these conditions of utilization, and the
 *	following stipulation of no guarantee shall be included in unchanged
 *	form inside the source code.
 *	(2) When this software is redistributed in a form in which it can be
 *	used in the development of other software, library form, etc., the above
 *	copyright display, these terms of utilization, and the following
 *	stipulation of no guarantee shall be inserted in documentation accompanying
 *	redistribution (user's manual, etc.).
 *	(3) When this software is redistributed in a form in which it cannot be used
 *	in the development of other software, embedded in devices, etc., one of the
 *	following conditions shall be satisfied.
 *		(a) The above copyright display, these terms of utilization, and the
 *		following stipulation of no guarantee shall be inserted in documentation
 *		accompanying redistribution (user's manual, etc.).
 *		(b) The TOPPERS Project shall be notified owing to a method in which the
 *		form of distribution is decided otherwise.
 *		(4) The above copyright holder and the TOPPERS Project shall be exempt
 *		from responsibility for whatever damages occur either directly or indirectly
 *		through the utilization of this software.
 *
 *	This software is something that is provided with no guarantee. The above copyright
 *	holder and the TOPPERS Project make no guarantee whatsoever in regard to this
 *	software, including the possibility of its application. In addition, the above
 *	copyright holder and the TOPPERS Project shall also not bear responsibility for
 *	whatever damages occur either directly or indirectly through the utilization of
 *	this software.
 *
 *	@(#) $Id: sys_config.c,v 1.5 2006/08/10 08:11:38 0684248 Exp $
 */

/*
 * Target system dependence module (for Integrator)
 */

#include "jsp_kernel.h"
/*
#include <integrator.h>
*/
#include <toya2.h>

/*interrupt mask*/
UW int_mask_table[MAX_INT_NUM]={
#if 0
	MASK_IRQ_SOFTINT,
	MASK_IRQ_UART0,
	MASK_IRQ_UART1,
	MASK_IRQ_KBDINT,
	MASK_IRQ_MOUSEINT,
	MASK_IRQ_TM0,
	MASK_IRQ_TM1,
	MASK_IRQ_TM2,
	MASK_IRQ_RTCINT,
	MASK_IRQ_EXPINT0,
	MASK_IRQ_EXPINT1,
	MASK_IRQ_EXPINT2,
	MASK_IRQ_EXPINT3,
	MASK_IRQ_PCIINT0,
	MASK_IRQ_PCIINT1,
	MASK_IRQ_PCIINT2,
	MASK_IRQ_PCIINT3,
	MASK_IRQ_LINT,
	MASK_IRQ_DEGINT,
	MASK_IRQ_ENUMINT,
	MASK_IRQ_PCILBINT,
	MASK_IRQ_EXTINT
#endif
};


/*
 * Table for interruption handler registration
 */
FP	 int_table[MAX_INT_NUM];

/*
 * 	QSC initialization
 */
void
init_clock(){
#if 0
	UW	  reg;

	/* Unlock CM_OSC */
	sil_wrw_mem((VP)CM_LOCK, LOCKVAL_UNLOCK);

	reg = sil_rew_mem((VP)CM_OSC);

	reg &= ~( LCLK_MASK | CORECLK_MASK);
	/* Sets base clock 50MHz CPU core clock 133MHz.  */
	reg |= LCLK_50MHZ | CORECLK_133MHZ;

	sil_wrw_mem((VP)CM_OSC, reg);

	/* Lock CM_OSC */
	sil_wrw_mem((VP)CM_LOCK, LOCKVAL_LOCK);
#endif
}


/*
 * Initialization related to interruption
 */
void
init_IRQ(){
	int i;

	/*
	 * initialize the interrupt table
	 */
	for(i = 0; i < MAX_INT_NUM; i++){
		int_table[i] = 0x00;		/* Reset */
	}

}


void
init_Toya2(){
	unsigned long	reg_wk;

	/* LED Initialize */
	rlMX21_PTA_DDIR |= 0xFF000000;	/* Set to "Output" 		 */
	rlMX21_PTA_GUIS |= 0xFF000000;	/* Set to "GPIO" 		 */
	rlMX21_PTA_OCR2 |= 0xFFFF0000;	/* Set to "DataRegister[i]"*/

	/* DMAC Initialize */
	rlMX21_PCCR0 |= (1<<30);		/* HCKL_DMA_EN: Enable 		*/
	rlMX21_PCCR0 |= (1<<13);		/* DMA_EN:		Enable 		*/
	rlMX21_DCR		= 0x00000005;	/* DAM:1, DRST:0, DEN:1 	*/
	rlMX21_DBTOCR	= 0x00000000;	/* Burst Timer-Out Disable 	*/
	rlMX21_RSSR0 = 3;				/* Request Source : Ext_DREQ*/

	rlMX21_PTA_DDIR |= (1<<22);	/* Set PA22 to "OUTPUT" */
	rlMX21_PTA_GUIS |= (1<<22);	/* Set to "GPIO" 		 	*/
	rlMX21_PTA_OCR2 &= ~(0x00003000);	/* Set to "A IN" */

	rlMX21_PTD_DDIR &= ~(1<<25);/* Set PD25 to "Input :A OUT" */
	rlMX21_PTD_GUIS |= (1<<25);	/* Set to "GPIO" 		 	*/
	rlMX21_PTD_ICONFA2 &= ~(0x000C0000);	/* Set to "A OUT=GPIO" */

	//
	// for PCMCIA/CF Slot
	rlMX21_PCCR0 |= (1<<11);	// Enable GPIO CLock
/* 2006/04/20 0M55B (new),when access to MX21_PTA_GUIS, it Abort at once.	Correction begin. Ver.1.10 */
 	/* rlMX21_PTF_GUIS 	|= 0x00617FFF; */ 	//set pcmcia used pins
/* 2006/04/20 0M55B (new),when access to MX21_PTA_GUIS, it Abort at once.	Correction End Ver.1.10 */
 	rlMX21_PTF_DDIR		|= 0x0061003F;	//configure pins to output
 	rlMX21_PTF_DDIR		&= 0xffff803f;	//configure pins to output (continued)
 	rlMX21_PTF_OCR1		&= 0x00cff000;
	rlMX21_PTF_OCR2		|= 0x00003c03;
	rlMX21_PTF_ICONFA1	=  0x00000000 ;
	rlMX21_PTF_ICONFA2	=  0x00000000 ;
	rlMX21_PTF_PUEN		=  0xFFFFFFFF;
	rlMX21_PTF_DR		&= 0xFFFEFFFF;
	rlMX21_PTF_DR		|= 0x00400000;
/* 2006/04/20 0M55B (new),when access to MX21_PTA_GUIS, it Abort at once.	Correction begin. Ver.1.10 */
 	rlMX21_PTF_GUIS 	|= 0x00617FFF; 	//set pcmcia used pins
/* 2006/04/20 0M55B (new),when access to MX21_PTA_GUIS, it Abort at once.	Correction End Ver.1.10 */

	rlMX21_PTA_GUIS		|= (1<<20);		// Set PTA20 To GPIO (CF_VCC)
	rlMX21_PTA_DDIR		|= (1<<20);		// Set PTA20 To Output
	rlMX21_PTA_OCR2		|= 0x00000300 ;	// Set PTA20 To GPIO_DR
	rlMX21_PTA_DR		&= ~(1<<20) ;	//  PTA20 Output LOW
	rlMX21_PTA_DR		|= (1<<20) ;	//  PTA20 Output HIGH

	rlMX21_PGCR |= 0x0002;				// Set to POE control validate

	/* Setting PCMCIA Memory Window */
	/* Window 0 = Attribute Memory Region 0x000 - 0x400 */
	reg_wk =
		(  0<<29 ) |	/* BSIZE: PCMCIA Valid 						*//* Invalid	 */
		(  0<<28 ) |	/* BSIZE: PCMCIA Write Protect Input Enable *//* Disable	 */
		(  0<<27 ) |	/* BSIZE: PCMCIA Write Protect Enable 		*//* Disable	 */
		(  2<<25 ) |	/* PRS:   PCMCIA Region Select 				*//* Attribute	 */
		(  0<<24 ) |	/* PPS:   PCMCIA Port Size 					*//* 16bit Width */
		(0x10<<17) |	/* PSL:   PCMCIA Strobe Length 				*/
		(0x08<<11) |	/* PSST:  PCMCIA Strobe Setup Time 			*/
		(0x08<< 5)		/* PSHT:  PCMCIA Strobe Hold Time 			*/
	;

	/* 2006/04/20 0M55B (new),when access to MX21_PTA_GUIS, it Abort at once.	Correction begin. Ver.1.10 */
#if 0
	if( rlMX21_SIDR3 == 0x101D101D ){
#else
	if( rlMX21_SIDR3 == 0x101D101D || rlMX21_SIDR3 == 0x201D101D ){
#endif
/* 2006/04/20 0M55B (new),when access to MX21_PTA_GUIS, it Abort at once.	Correction End Ver.1.10 */
		// When MASK M55B
		reg_wk |= 0x05; /* BSIZE: PCMCIA Bank Size 					*//* 1 kbyte	*/
	}
	else
	{	// When MASK 2L45X
		reg_wk |= 0x0F; /* BSIZE: PCMCIA Bank Size 					*//* 1 kbyte	*/
	}


	rlMX21_POR0  = reg_wk ;	/* set to Option Register 0 */
	rlMX21_POFR0 = 0x000;		/* Offset Address 	*/
	rlMX21_PBR0  = 0x000;		/* BASE Address: D4000000 & 07FF */
	rlMX21_POR0 |= (1<<29) ;

	/* Window 1 = I/O Region 0x400 - 0x40F (16Bytes) */
	reg_wk =
		(  0<<29 ) |	/* BSIZE: PCMCIA Valid 						*//* Invalid	 */
		(  0<<28 ) |	/* BSIZE: PCMCIA Write Protect Input Enable *//* Disable	 */
		(  0<<27 ) |	/* BSIZE: PCMCIA Write Protect Enable 		*//* Disable	 */
		(  0<<25 ) |	/* PRS:   PCMCIA Region Select 				*//* Common Space*/
		(  0<<24 ) |	/* PPS:   PCMCIA Port Size 					*//* 16bit Width */
		(0x10<<17) |	/* PSL:   PCMCIA Strobe Length 				*/
		(0x08<<11) |	/* PSST:  PCMCIA Strobe Setup Time 			*/
		(0x08<< 5)		/* PSHT:  PCMCIA Strobe Hold Time 			*/
	;

/* 2006/04/20 0M55B (new),when access to MX21_PTA_GUIS, it Abort at once.	Correction begin. Ver.1.10 */
#if 0
	if( rlMX21_SIDR3 == 0x101D101D ){
#else
	if( rlMX21_SIDR3 == 0x101D101D || rlMX21_SIDR3 == 0x201D101D ){
#endif
/* 2006/04/20 0M55B (new),when access to MX21_PTA_GUIS, it Abort at once.	Correction End Ver.1.10 */
		// When MASK M55B
		reg_wk |= 0x07; /* BSIZE: PCMCIA Bank Size 					*//* 16 byte	*/
	}
	else
	{	// When MASK 2L45X
		reg_wk |= 0x0D; /* BSIZE: PCMCIA Bank Size 					*//* 16 byte	*/
	}

	rlMX21_POR1  = reg_wk ;	/* set to Option Register 0 */
	rlMX21_POFR1 = 0x000;		/* Offset Address 	*/
	rlMX21_PBR1  = 0x400;		/* BASE Address: D4000400 & 07FF */
	rlMX21_POR1 |= (1<<29) ;
}

/*
 * Initialization of the target system dependency
 */
void
sys_initialize()
{
	init_clock();

	init_IRQ();

	/*
	 * Mapping SSRAM to 0x00000000
	 */
#if 0
	sil_wrw_mem((VP)CM_CTRL,CM_CTRL_REMAP);
#endif
	/*
	 * The interrupt handler is registered to the vector table of ARM.
	 */
//	  arm_install_handler(IRQ_Number, IRQ_Handler);

	/*
	 * UART is initialized so that sys_putc may become possible.
	 */
	init_uart();
	init_Toya2();

}


/*
 * Completion of target system
 */
void
sys_exit(void)
{
	syslog(LOG_EMERG, "End Kernel.....!");
	while(1);
}


/*
 * Output of character of target system
 */

void
sys_putc(char c)
{
	if (c == '\n') {
		uart_putc('\r');
	}
	uart_putc(c);
}


/*
 *	Set interrupt handler
 *
 *	Set the start address of the interrupt handler of interruption number inhno to inthdr.
 */
void
define_inh(INHNO inhno, FP inthdr)
{
	assert(inhno < MAX_INT_NUM);
	int_table[inhno] = inthdr;

}

/*
 * Processing when undefined interruption occured
 */
void
undef_interrupt(){
	syslog(LOG_EMERG, "Unregistered Interrupt occurs.");
	while(1);
}


/* It waits until the IRQ register is cleared.	*/
#define INT_CLEAR_DELAY  0x70
void poll_intreg(int int_mask)
{
	int i;

	//while(*IRQ0_ENABLESET & int_mask);
	for(i=0;i<INT_CLEAR_DELAY;i++);
	enaint();

}

ER ena_int(UINT intno)
{

	if (((intno < IRQ_CSPI3_BIT)	  || (intno > IRQ_DMACH15_BIT)) &&
		((intno < IRQ_EMMAEN_BIT)	  || (intno > IRQ_LCDC_BIT)))
		return E_PAR;

		sil_wrw_mem((VP)(DMX21_REG_AITC_BASE+0x08),intno);

	return E_OK;
}



ER dis_int(UINT intno)
{

	if (((intno < IRQ_CSPI3_BIT)	  || (intno > IRQ_DMACH15_BIT)) &&
		((intno < IRQ_EMMAEN_BIT)	  || (intno > IRQ_LCDC_BIT)))
		return E_PAR;

		sil_wrw_mem((VP)(DMX21_REG_AITC_BASE+0x0C),intno);

	return E_OK;
}