📄 toya2.h
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* UART1 Control Registers
*/
#define UART1_DR (UART1_BASE_REG)
#define UART1_RSR (UART1_BASE_REG + 0x04)
#define UART1_ECR (UART1_BASE_REG + 0x04)
#define UART1_LCRH (UART1_BASE_REG + 0x08)
#define UART1_LCRM (UART1_BASE_REG + 0x0C)
#define UART1_LCRL (UART1_BASE_REG + 0x10)
#define UART1_CR (UART1_BASE_REG + 0x14)
#define UART1_FR (UART1_BASE_REG + 0x18)
#define UART1_IIR (UART1_BASE_REG + 0x1C)
#define UART1_ICR (UART1_BASE_REG + 0x1C)
/*
* Receive Error Constants : UARTx_RSR
*/
#define URSR_OVERRUN 0x8
#define URSR_BREAK 0x4
#define URSR_PARITY 0x2
#define URSR_FRAMING 0x1
/*
* Line Control Constants: UARTx_LCRH
*/
/*[6:5] Word Length*/
#define ULCRH_WLEN_8BIT 0x60
#define ULCRH_WLEN_7BIT 0x40
#define ULCRH_WLEN_6BIT 0x20
#define ULCRH_WLEN_5BIT 0x00
/*[4] FIFO*/
#define ULCRH_FEN 0x10
/*[3] Stop Bit*/
#define ULCRH_STP2 0x08
/*[2] Even Parity Select*/
#define ULCRH_EPS 0x04
/*[1] Parity Enable*/
#define ULCRH_PEN 0x02
/*[0] Send Break*/
#define ULCRH_BRK 0x01
/*
* Line Control Constants: UARTx_LCRM
*/
/*[7:0] Baud Rate*/
#define ULCRM_460800 0x00
#define ULCRL_460800 0x01
#define ULCRM_230400 0x00
#define ULCRL_230400 0x03
#define ULCRM_115200 0x00
#define ULCRL_115200 0x07
#define ULCRM_76800 0x00
#define ULCRL_76800 0x0B
#define ULCRM_57600 0x00
#define ULCRL_57600 0x0F
#define ULCRM_38400 0x0
#define ULCRL_38400 0x17
#define ULCRM_19200 0x00
#define ULCRL_19200 0x2F
#define ULCRM_14400 0x00
#define ULCRL_14400 0x3F
#define ULCRM_9600 0x0
#define ULCRL_9600 0x5F
#define ULCRM_2400 0x00
#define ULCRL_2400 0x7F
#define ULCRM_1200 0x00
#define ULCRL_1200 0xFF
/*
* Control Register Constants : UARTx_CR
*/
/*[7] Loop Back Enable*/
#define UCR_LBE 0x80
/*[6] Receive Timeout Interrupt Enable*/
#define UCR_RTIE 0x40
/*[5] Transmit Interrupt Enable*/
#define UCR_TIE 0x20
/*[4] Receive Interrupt Enable*/
#define UCR_RIE 0x10
/*[3] Modem Status Interrupt Enable*/
#define UCR_MSIE 0x08
/*[0] UART Enable*/
#define UCR_UARTEN 0x01
/*
* Flag Register Constants : UARTx_FR
*/
/*[7] Transmit FIFO Empty*/
#define UFR_TXFE 0x80
/*[6] Receive FIFO Full*/
#define UFR_RXFF 0x40
/*[5] Transmit FIFO Full*/
#define UFR_TXFF 0x20
/*[4] Receive FIFO Empty*/
#define UFR_RXFE 0x10
/*[3] UART Busy*/
#define UFR_BUSY 0x08
/*[2] Data Carrier Detect*/
#define UFR_DCD 0x04
/*[1] Data Set Ready*/
#define UFR_DSR 0x02
/*[0] Clear To Send*/
#define UFR_CTS 0x01
/*
* Interrupt Identifier Constantse: UARTx_IIR
*/
/*[3] Receive Timeout Interrupt Status*/
#define IIR_TRIS 0x08
/*[2] Transmit Interrupt Status*/
#define IIR_TIS 0x04
/*[1] Receive Interrupt Status*/
#define IIR_RIS 0x02
/*[0] Modem Interrupt Status*/
#define IIR_MIS 0x01
#endif
#ifndef _MACRO_ONLY
/*
* For build in UART,simplified SIO driver
*/
/*
* Initialization for kernel's starting(To use sys_putc. )
*/
extern void init_uart(void);
/*
* Serial I/O port initialization block
*/
typedef struct sio_port_initialization_block
{
VP uart_data;
VP uart_control;
VP linectrl_lo;
VP linectrl_mid;
VP linectrl_hi;
VP int_identifier;
VP flag_register;
VW irq_bit;
}
SIOPINIB;
/*
* Definition for serial I/O port management block
*/
typedef struct sio_port_control_block
{
const SIOPINIB *siopinib; /* Serial I/O port initialization block */
VP_INT exinf; /* Extension information */
BOOL openflag; /* Already opened flag */
BOOL sendflag; /* The transmit interrupt is enabled flag */
BOOL getready; /* The state that the character was received. */
BOOL putready; /* The statte that it is capable to transmit character */
}SIOPCB;
/*
* Identify number of the call back routine
*/
#define SIO_ERDY_SND 1u /* Transmissive callback */
#define SIO_ERDY_RCV 2u /* Reception notification callback */
/*
* Polling output from the on-chip UART
*/
extern void uart_putc(char c);
/*
* SIO driver intialization routine
*/
extern void uart_initialize(void);
/*
* Is there any port opened?
*/
extern BOOL uart_openflag(void);
/*
* Open the serial I/O port
*/
extern SIOPCB *uart_opn_por(ID siopid, VP_INT exinf);
/*
* Close the serial I/O port
*/
extern void uart_cls_por(SIOPCB *siopcb);
/*
* Character transmission to the serial I/O port
*/
extern BOOL uart_snd_chr(SIOPCB *siopcb, char c);
/*
* Character reception from th eserial I/O port
*/
extern INT uart_rcv_chr(SIOPCB *siopcb);
/*
* Enable the callback from serial I/O port
*/
extern void uart_ena_cbr(SIOPCB *siopcb, UINT cbrtn);
/*
* Disable the callback from serial I/O port
*/
extern void uart_dis_cbr(SIOPCB *siopcb, UINT cbrtn);
/*
* SIO driver intialization routine
*/
extern void uart_in_isr(void);
extern void uart_out_isr(void);
/*
* Transmissive callback from the Serial I/O port
*/
extern void uart_ierdy_snd(VP_INT exinf);
/*
* Reception notification callback from the Serial I/O port
*/
extern void uart_ierdy_rcv(VP_INT exinf);
#endif /* _MACRO_ONLY */
#endif /* _INTEGRATOR_H_ */
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