📄 toya2.h
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/*
* The above copyright holder, limited to cases in which one satisfies
* conditions (1) ~ (4) below, or the conditions described in Version 2
* of of the GNU Public License officially announced by the Free Software
* Foundation, consents to the use, reproduction, alteration, and
* redistribution (hereafter called utilization) of this software (this
* software includes alterations, likewise below) without compensation.
*
* (1) When this software is utilized in the form of source code, the
* above copyright declaration, these conditions of utilization, and the
* following stipulation of no guarantee shall be included in unchanged
* form inside the source code.
* (2) When this software is redistributed in a form in which it can be
* used in the development of other software, library form, etc., the above
* copyright display, these terms of utilization, and the following
* stipulation of no guarantee shall be inserted in documentation accompanying
* redistribution (user's manual, etc.).
* (3) When this software is redistributed in a form in which it cannot be used
* in the development of other software, embedded in devices, etc., one of the
* following conditions shall be satisfied.
* (a) The above copyright display, these terms of utilization, and the
* following stipulation of no guarantee shall be inserted in documentation
* accompanying redistribution (user's manual, etc.).
* (b) The TOPPERS Project shall be notified owing to a method in which the
* form of distribution is decided otherwise.
* (4) The above copyright holder and the TOPPERS Project shall be exempt
* from responsibility for whatever damages occur either directly or indirectly
* through the utilization of this software.
*
* This software is something that is provided with no guarantee. The above copyright
* holder and the TOPPERS Project make no guarantee whatsoever in regard to this
* software, including the possibility of its application. In addition, the above
* copyright holder and the TOPPERS Project shall also not bear responsibility for
* whatever damages occur either directly or indirectly through the utilization of
* this software.
*
* @(#) $Id: toya2.h,v 1.2 2006/07/21 09:50:18 9564907 Exp $
*/
#ifndef _TOYA2_H_
#define _TOYA2_H_
#ifndef _MACRO_ONLY
#include <itron.h>
#include <sil.h>
#endif /* _MACRO_ONLY */
#include "armv4.h"
#include "sys_config.h"
#include "cpu_config.h"
#include "reg_mx21.h"
/*
* Integrator AP Peripheral Base Address (Toya2)
*
*/
#define IRQ_BASE_REG 0x10040000
//#define UART0_BASE_REG 0x16000000
//#define UART1_BASE_REG 0x17000000
/*
* Interrupt Control Registers
*/
#define IRQ0_STATUS_H (IRQ_BASE_REG + 0x48)
#define IRQ0_STATUS_L (IRQ_BASE_REG + 0x4C)
//#define IRQ0_RAWSTAT (IRQ_BASE_REG + 0x04)
#define IRQ0_ENABLEREG_H (IRQ_BASE_REG + 0x10)
#define IRQ0_ENABLEREG_L (IRQ_BASE_REG + 0x14)
/* Interrupt Assignments Low */
#define IRQ_CSPI3_BIT 6 /* Configurable SPI(CSPI3) */
#define IRQ_SRCL_BIT 7 /* Random Number generator Accelerator(RNGA) */
#define IRQ_GPIO_BIT 8 /* General purpose Input/Output(GPIO) */
#define IRQ_FIRI_BIT 9 /* Fast Infra Red Interface(FIRI) */
#define IRQ_SDHC2_BIT 10 /* Secure Digital Host Controller(SDHC2) */
#define IRQ_SDHC1_BIT 11 /* Secure Digital Host Controller(SDHC1) */
#define IRQ_I2C_BIT 12 /* I2C Bus Controller(I2C) */
#define IRQ_SS2_BIT 13 /* Synchronous Serial Interface(SSI2) */
#define IRQ_SS1_BIT 14 /* Synchronous Serial Interface(SSI1) */
#define IRQ_CSPI2_BIT 15 /* Configurable SPI(CSPI2) */
#define IRQ_CSPI1_BIT 16 /* Configurable SPI(CSPI1) */
#define IRQ_UART3_BIT 17 /* UART4 */
#define IRQ_UART2_BIT 18 /* UART3 */
#define IRQ_UART1_BIT 19 /* UART2 */
#define IRQ_UART0_BIT 20 /* UART1 */
#define IRQ_KPP_BIT 21 /* Key Pad Port(KPP) */
#define IRQ_RTC_BIT 22 /* Real-Time Clock(RTC) */
#define IRQ_PWM_BIT 23 /* Pulse Width Modulator(PWM) */
#define IRQ_GPT3_BIT 24 /* General Purpose Timer(GPT3) */
#define IRQ_GPT2_BIT 25 /* General Purpose Timer(GPT2) */
#define IRQ_GPT1_BIT 26 /* General Purpose Timer(GPT1) */
#define IRQ_WDOG_BIT 27 /* Watchdog(WDOG) */
#define IRQ_PCMCIA_BIT 28 /* PCMCIA/CF Host Controller(PCMCIA) */
#define IRQ_NFC_BIT 29 /* Nand Flash Controller(NFC) */
#define IRQ_BMI_BIT 30 /* Bus Master interface(BMI) */
#define IRQ_CSI_BIT 31 /* CMOS Sensor Interface(CSI) */
/* Interrupt Assignments High */
#define IRQ_DMACH0_BIT 32 /* DMA Channel 0 Interrupt */
#define IRQ_DMACH1_BIT 33 /* DMA Channel 1 Interrupt */
#define IRQ_DMACH2_BIT 34 /* DMA Channel 2 Interrupt */
#define IRQ_DMACH3_BIT 35 /* DMA Channel 3 Interrupt */
#define IRQ_DMACH4_BIT 36 /* DMA Channel 4 Interrupt */
#define IRQ_DMACH5_BIT 37 /* DMA Channel 5 Interrupt */
#define IRQ_DMACH6_BIT 38 /* DMA Channel 6 Interrupt */
#define IRQ_DMACH7_BIT 39 /* DMA Channel 7 Interrupt */
#define IRQ_DMACH8_BIT 40 /* DMA Channel 8 Interrupt */
#define IRQ_DMACH9_BIT 41 /* DMA Channel 9 Interrupt */
#define IRQ_DMACH10_BIT 42 /* DMA Channel 10 Interrupt */
#define IRQ_DMACH11_BIT 43 /* DMA Channel 11 Interrupt */
#define IRQ_DMACH12_BIT 44 /* DMA Channel 12 Interrupt */
#define IRQ_DMACH13_BIT 45 /* DMA Channel 13 Interrupt */
#define IRQ_DMACH14_BIT 46 /* DMA Channel 14 Interrupt */
#define IRQ_DMACH15_BIT 47 /* DMA Channel 15 Interrupt */
/* Reserve */
#define IRQ_EMMAEN_BIT 49 /* eMMA Encoder Interrupt */
#define IRQ_EMMADE_BIT 50 /* eMMA Decoder Interrupt */
#define IRQ_EMMAPR_BIT 51 /* eMMA Pre Processor Interrupt */
#define IRQ_EMMAPP_BIT 52 /* eMMA Post Processor Interrupt */
#define IRQ_USBWKU_BIT 53 /* USBOTG Wakeup Interrupt */
#define IRQ_USBDMA_BIT 54 /* USBOTG DMA Interrupt */
#define IRQ_USBHOST_BIT 55 /* USBOTG Host Interrupt */
#define IRQ_USBFUNC_BIT 56 /* USBOTG Function Interrupt */
#define IRQ_USBMNP_BIT 57 /* USBOTG HNP Interrupt */
#define IRQ_USBCTRL_BIT 58 /* USBOTG Control interrupt */
#define IRQ_SRCH_BIT 59 /* Run-Time Integrity Checker(RTIC) */
#define IRQ_SLCDC_BIT 60 /* Smart LCD Controller(SLCDC) */
#define IRQ_LCDC_BIT 61 /* LCD Controller(LCDC) */
/* Interrupt Assignments Low */
#define IRQ_CSPI3 (1 << IRQ_CSPI3_BIT) /* Configurable SPI(CSPI3) */
#define IRQ_SRCL (1 << IRQ_SRCL_BIT) /* Random Number generator Accelerator(RNGA) */
#define IRQ_GPIO (1 << IRQ_GPIO_BIT) /* General purpose Input/Output(GPIO) */
#define IRQ_FIRI (1 << IRQ_FIRI_BIT) /* Fast Infra Red Interface(FIRI) */
#define IRQ_SDHC2 (1 << IRQ_SDHC2_BIT) /* Secure Digital Host Controller(SDHC2) */
#define IRQ_SDHC1 (1 << IRQ_SDHC1_BIT) /* Secure Digital Host Controller(SDHC1) */
#define IRQ_I2C (1 << IRQ_I2C_BIT) /* I2C Bus Controller(I2C) */
#define IRQ_SS2 (1 << IRQ_SS2_BIT) /* Synchronous Serial Interface(SSI2) */
#define IRQ_SS1 (1 << IRQ_SS1_BIT) /* Synchronous Serial Interface(SSI1) */
#define IRQ_CSPI2 (1 << IRQ_CSPI2_BIT) /* Configurable SPI(CSPI2) */
#define IRQ_CSPI1 (1 << IRQ_CSPI1_BIT) /* Configurable SPI(CSPI1) */
#define IRQ_UART3 (1 << IRQ_UART3_BIT) /* UART4 */
#define IRQ_UART2 (1 << IRQ_UART2_BIT) /* UART3 */
#define IRQ_UART1 (1 << IRQ_UART1_BIT) /* UART2 */
#define IRQ_UART0 (1 << IRQ_UART0_BIT) /* UART1 */
#define IRQ_KPP (1 << IRQ_KPP_BIT) /* Key Pad Port(KPP) */
#define IRQ_RTC (1 << IRQ_RTC_BIT) /* Real-Time Clock(RTC) */
#define IRQ_PWM (1 << IRQ_PWM_BIT) /* Pulse Width Modulator(PWM) */
#define IRQ_GPT3 (1 << IRQ_GPT3_BIT) /* General Purpose Timer(GPT3) */
#define IRQ_GPT2 (1 << IRQ_GPT2_BIT) /* General Purpose Timer(GPT2) */
#define IRQ_GPT1 (1 << IRQ_GPT1_BIT) /* General Purpose Timer(GPT1) */
#define IRQ_WDOG (1 << IRQ_WDOG_BIT) /* Watchdog(WDOG) */
#define IRQ_PCMCIA (1 << IRQ_PCMCIA_BIT) /* PCMCIA/CF Host Controller(PCMCIA) */
#define IRQ_NFC (1 << IRQ_NFC_BIT) /* Nand Flash Controller(NFC) */
#define IRQ_BMI (1 << IRQ_BMI_BIT) /* Bus Master interface(BMI) */
#define IRQ_CSI (1 << IRQ_CSI_BIT) /* CMOS Sensor Interface(CSI) */
/* Interrupt Assignments High */
#define IRQ_DMACH0 (1 << (IRQ_DMACH0_BIT-32)) /* DMA Channel 0 Interrupt */
#define IRQ_DMACH1 (1 << (IRQ_DMACH1_BIT-32)) /* DMA Channel 1 Interrupt */
#define IRQ_DMACH2 (1 << (IRQ_DMACH2_BIT-32)) /* DMA Channel 2 Interrupt */
#define IRQ_DMACH3 (1 << (IRQ_DMACH3_BIT-32)) /* DMA Channel 3 Interrupt */
#define IRQ_DMACH4 (1 << (IRQ_DMACH4_BIT-32)) /* DMA Channel 4 Interrupt */
#define IRQ_DMACH5 (1 << (IRQ_DMACH5_BIT-32)) /* DMA Channel 5 Interrupt */
#define IRQ_DMACH6 (1 << (IRQ_DMACH6_BIT-32)) /* DMA Channel 6 Interrupt */
#define IRQ_DMACH7 (1 << (IRQ_DMACH7_BIT-32)) /* DMA Channel 7 Interrupt */
#define IRQ_DMACH8 (1 << (IRQ_DMACH8_BIT-32)) /* DMA Channel 8 Interrupt */
#define IRQ_DMACH9 (1 << (IRQ_DMACH9_BIT-32)) /* DMA Channel 9 Interrupt */
#define IRQ_DMACH10 (1 << (IRQ_DMACH10_BIT-32)) /* DMA Channel 10 Interrupt */
#define IRQ_DMACH11 (1 << (IRQ_DMACH11_BIT-32)) /* DMA Channel 11 Interrupt */
#define IRQ_DMACH12 (1 << (IRQ_DMACH12_BIT-32)) /* DMA Channel 12 Interrupt */
#define IRQ_DMACH13 (1 << (IRQ_DMACH13_BIT-32)) /* DMA Channel 13 Interrupt */
#define IRQ_DMACH14 (1 << (IRQ_DMACH14_BIT-32)) /* DMA Channel 14 Interrupt */
#define IRQ_DMACH15 (1 << (IRQ_DMACH15_BIT-32)) /* DMA Channel 15 Interrupt */
/* Reserve */
#define IRQ_EMMAEN (1 << (IRQ_EMMAEN_BIT-32)) /* eMMA Encoder Interrupt */
#define IRQ_EMMADE (1 << (IRQ_EMMADE_BIT-32)) /* eMMA Decoder Interrupt */
#define IRQ_EMMAPR (1 << (IRQ_EMMAPR_BIT-32)) /* eMMA Pre Processor Interrupt */
#define IRQ_EMMAPP (1 << (IRQ_EMMAPP_BIT-32)) /* eMMA Post Processor Interrupt */
#define IRQ_USBWKU (1 << (IRQ_USBWKU_BIT-32)) /* USBOTG Wakeup Interrupt */
#define IRQ_USBDMA (1 << (IRQ_USBDMA_BIT-32)) /* USBOTG DMA Interrupt */
#define IRQ_USBHOST (1 << (IRQ_USBHOST_BIT-32)) /* USBOTG Host Interrupt */
#define IRQ_USBFUNC (1 << (IRQ_USBFUNC_BIT-32)) /* USBOTG Function Interrupt */
#define IRQ_USBMNP (1 << (IRQ_USBMNP_BIT-32)) /* USBOTG HNP Interrupt */
#define IRQ_USBCTRL (1 << (IRQ_USBCTRL_BIT-32)) /* USBOTG Control interrupt */
#define IRQ_SRCH (1 << (IRQ_SRCH_BIT-32)) /* Run-Time Integrity Checker(RTIC) */
#define IRQ_SLCDC (1 << (IRQ_SLCDC_BIT-32)) /* Smart LCD Controller(SLCDC) */
#define IRQ_LCDC (1 << (IRQ_LCDC_BIT-32)) /* LCD Controller(LCDC) */
/*
* Timer2 has has the highest priority ??
*/
#if 0
#define MASK_IRQ_TM2 0x3FFFFF
#define MASK_IRQ_TM1 0x3FFF7F
#define MASK_IRQ_TM0 0x3FFF3F
#define MASK_IRQ_MOUSEINT 0x3FFF1F
#define MASK_IRQ_KBDINT 0x3FFF0F
#define MASK_IRQ_UART1 0x3FFF07
#define MASK_IRQ_UART0 0x3FFF03
#define MASK_IRQ_SOFTINT 0x3FFF01
#define MASK_IRQ_EXTINT 0x3FFF00
#define MASK_IRQ_PCILBINT 0x1FFF00
#define MASK_IRQ_ENUMINT 0x0FFF00
#define MASK_IRQ_DEGINT 0x07FF00
#define MASK_IRQ_LINT 0x03FF00
#define MASK_IRQ_PCIINT3 0x01FF00
#define MASK_IRQ_PCIINT2 0x00FF00
#define MASK_IRQ_PCIINT1 0x007F00
#define MASK_IRQ_PCIINT0 0x003F00
#define MASK_IRQ_EXPINT3 0x001F00
#define MASK_IRQ_EXPINT2 0x000F00
#define MASK_IRQ_EXPINT1 0x000700
#define MASK_IRQ_EXPINT0 0x000300
#define MASK_IRQ_RTCINT 0x000100
#define INT_DISABLE_ALL 0x3FFFFF
#endif
#if 0
/*
* UART0 Control Registers
*/
#define UART0_DR (UART0_BASE_REG)
#define UART0_RSR (UART0_BASE_REG + 0x04)
#define UART0_ECR (UART0_BASE_REG + 0x04)
#define UART0_LCRH (UART0_BASE_REG + 0x08)
#define UART0_LCRM (UART0_BASE_REG + 0x0C)
#define UART0_LCRL (UART0_BASE_REG + 0x10)
#define UART0_CR (UART0_BASE_REG + 0x14)
#define UART0_FR (UART0_BASE_REG + 0x18)
#define UART0_IIR (UART0_BASE_REG + 0x1C)
#define UART0_ICR (UART0_BASE_REG + 0x1C)
/*
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