📄 newreg72v05.h
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#define REG08_IDE_WrRegValue_L (volatile UCHAR *)(REG_BASE + 0xA5) /* IDE Register Write Value Low */
#else /* #ifdef LITTLE_ENDIAN_C */
/*==========================================================================================================/
/ Register 8bit Access Define /
/==========================================================================================================*/
/*---------------/
Common block /
/---------------*/
#define REG08_MainIntStat (volatile UCHAR *)(REG_BASE + 0x00) /* Main Interrupt Status */
#define REG08_DeviceIntStat (volatile UCHAR *)(REG_BASE + 0x01) /* EPr Interrupt Status */
#define REG08_HostIntStat (volatile UCHAR *)(REG_BASE + 0x02) /* SIE Interrupt Status */
#define REG08_CPU_IntStat (volatile UCHAR *)(REG_BASE + 0x03) /* CPU Interrupt Status */
#define REG08_IDE_IntStat (volatile UCHAR *)(REG_BASE + 0x04) /* IDE Interrupt Status */
#define REG08_MediaFIFO_IntStat (volatile UCHAR *)(REG_BASE + 0x05) /* Media FIFO Interrupt Status */
#define REG08_MainIntEnb (volatile UCHAR *)(REG_BASE + 0x10) /* Main Interrupt Enable */
#define REG08_DeviceIntEnb (volatile UCHAR *)(REG_BASE + 0x11) /* EPr Interrupt Enable */
#define REG08_HostIntEnb (volatile UCHAR *)(REG_BASE + 0x12) /* SIE Interrupt Enable */
#define REG08_CPU_IntEnb (volatile UCHAR *)(REG_BASE + 0x13) /* CPU Interrupt Enable */
#define REG08_IDE_IntEnb (volatile UCHAR *)(REG_BASE + 0x14) /* IDE Interrupt Enable */
#define REG08_MediaFIFO_IntEnb (volatile UCHAR *)(REG_BASE + 0x15) /* Media FIFO Interrupt Enable */
#define REG08_RevisionNum (volatile UCHAR *)(REG_BASE + 0x20) /* Revision Number */
#define REG08_ChipReset (volatile UCHAR *)(REG_BASE + 0x21) /* Chip Reset */
#define REG08_PM_Control_0 (volatile UCHAR *)(REG_BASE + 0x22) /* Power Management Control 0 */
#define REG08_PM_Control_1 (volatile UCHAR *)(REG_BASE + 0x23) /* Power Management Control 1 */
#define REG08_WakeupTim_H (volatile UCHAR *)(REG_BASE + 0x24) /* Wake Up Timer High */
#define REG08_WakeupTim_L (volatile UCHAR *)(REG_BASE + 0x25) /* Wake Up Timer Low */
#define REG08_H_USB_Control (volatile UCHAR *)(REG_BASE + 0x26) /* Host USB Control */
#define REG08_H_XcvrControl (volatile UCHAR *)(REG_BASE + 0x27) /* Host Xcvr Control */
#define REG08_D_USB_Status (volatile UCHAR *)(REG_BASE + 0x28) /* Device USB Status */
#define REG08_H_USB_Status (volatile UCHAR *)(REG_BASE + 0x29) /* Host USB Status */
#define REG08_FIFO_Rd_0 (volatile UCHAR *)(REG_BASE + 0x30) /* FIFO Read High */
#define REG08_FIFO_Rd_1 (volatile UCHAR *)(REG_BASE + 0x31) /* FIFO Read Low */
#define REG08_FIFO_Wr_0 (volatile UCHAR *)(REG_BASE + 0x32) /* FIFO Write High */
#define REG08_FIFO_Wr_1 (volatile UCHAR *)(REG_BASE + 0x33) /* FIFO Write Low */
#define REG08_FIFO_RdRemain_H (volatile UCHAR *)(REG_BASE + 0x34) /* FIFO Read Remain High */
#define REG08_FIFO_RdRemain_L (volatile UCHAR *)(REG_BASE + 0x35) /* FIFO Read Remain Low */
#define REG08_FIFO_WrRemain_H (volatile UCHAR *)(REG_BASE + 0x36) /* FIFO Write Remain High */
#define REG08_FIFO_WrRemain_L (volatile UCHAR *)(REG_BASE + 0x37) /* FIFO Write Remain Low */
#define REG08_FIFO_ByteRd (volatile UCHAR *)(REG_BASE + 0x38) /* FIFO Byte Read */
#define REG08_RAM_RdAdrs_H (volatile UCHAR *)(REG_BASE + 0x40) /* RAM Read Address High */
#define REG08_RAM_RdAdrs_L (volatile UCHAR *)(REG_BASE + 0x41) /* RAM Read Address Low */
#define REG08_RAM_RdControl (volatile UCHAR *)(REG_BASE + 0x42) /* RAM Read Control */
#define REG08_RAM_RdCount (volatile UCHAR *)(REG_BASE + 0x43) /* RAM Read Counter */
#define REG08_RAM_WrAdrs_H (volatile UCHAR *)(REG_BASE + 0x44) /* RAM Write Address High */
#define REG08_RAM_WrAdrs_L (volatile UCHAR *)(REG_BASE + 0x45) /* RAM Write Address Low */
#define REG08_RAM_WrDoor_0 (volatile UCHAR *)(REG_BASE + 0x46) /* RAM Write Door High */
#define REG08_RAM_WrDoor_1 (volatile UCHAR *)(REG_BASE + 0x47) /* RAM Write Door Low */
#define REG08_MediaFIFO_Control (volatile UCHAR *)(REG_BASE + 0x48) /* Media FIFO Clear */
#define REG08_ClrAllMediaFIFO_Join (volatile UCHAR *)(REG_BASE + 0x49) /* Clear All Media FIFO Join */
#define REG08_MediaFIFO_Join (volatile UCHAR *)(REG_BASE + 0x4A) /* Media FIFO Join */
#define REG08_RAM_Rd_00 (volatile UCHAR *)(REG_BASE + 0x50) /* RAM Read 00 */
#define REG08_RAM_Rd_01 (volatile UCHAR *)(REG_BASE + 0x51) /* RAM Read 01 */
#define REG08_RAM_Rd_02 (volatile UCHAR *)(REG_BASE + 0x52) /* RAM Read 02 */
#define REG08_RAM_Rd_03 (volatile UCHAR *)(REG_BASE + 0x53) /* RAM Read 03 */
#define REG08_RAM_Rd_04 (volatile UCHAR *)(REG_BASE + 0x54) /* RAM Read 04 */
#define REG08_RAM_Rd_05 (volatile UCHAR *)(REG_BASE + 0x55) /* RAM Read 05 */
#define REG08_RAM_Rd_06 (volatile UCHAR *)(REG_BASE + 0x56) /* RAM Read 06 */
#define REG08_RAM_Rd_07 (volatile UCHAR *)(REG_BASE + 0x57) /* RAM Read 07 */
#define REG08_RAM_Rd_08 (volatile UCHAR *)(REG_BASE + 0x58) /* RAM Read 08 */
#define REG08_RAM_Rd_09 (volatile UCHAR *)(REG_BASE + 0x59) /* RAM Read 09 */
#define REG08_RAM_Rd_0A (volatile UCHAR *)(REG_BASE + 0x5A) /* RAM Read 0A */
#define REG08_RAM_Rd_0B (volatile UCHAR *)(REG_BASE + 0x5B) /* RAM Read 0B */
#define REG08_RAM_Rd_0C (volatile UCHAR *)(REG_BASE + 0x5C) /* RAM Read 0C */
#define REG08_RAM_Rd_0D (volatile UCHAR *)(REG_BASE + 0x5D) /* RAM Read 0D */
#define REG08_RAM_Rd_0E (volatile UCHAR *)(REG_BASE + 0x5E) /* RAM Read 0E */
#define REG08_RAM_Rd_0F (volatile UCHAR *)(REG_BASE + 0x5F) /* RAM Read 0F */
#define REG08_RAM_Rd_10 (volatile UCHAR *)(REG_BASE + 0x60) /* RAM Read 10 */
#define REG08_RAM_Rd_11 (volatile UCHAR *)(REG_BASE + 0x61) /* RAM Read 11 */
#define REG08_RAM_Rd_12 (volatile UCHAR *)(REG_BASE + 0x62) /* RAM Read 12 */
#define REG08_RAM_Rd_13 (volatile UCHAR *)(REG_BASE + 0x63) /* RAM Read 13 */
#define REG08_RAM_Rd_14 (volatile UCHAR *)(REG_BASE + 0x64) /* RAM Read 14 */
#define REG08_RAM_Rd_15 (volatile UCHAR *)(REG_BASE + 0x65) /* RAM Read 15 */
#define REG08_RAM_Rd_16 (volatile UCHAR *)(REG_BASE + 0x66) /* RAM Read 16 */
#define REG08_RAM_Rd_17 (volatile UCHAR *)(REG_BASE + 0x67) /* RAM Read 17 */
#define REG08_RAM_Rd_18 (volatile UCHAR *)(REG_BASE + 0x68) /* RAM Read 18 */
#define REG08_RAM_Rd_19 (volatile UCHAR *)(REG_BASE + 0x69) /* RAM Read 19 */
#define REG08_RAM_Rd_1A (volatile UCHAR *)(REG_BASE + 0x6A) /* RAM Read 1A */
#define REG08_RAM_Rd_1B (volatile UCHAR *)(REG_BASE + 0x6B) /* RAM Read 1B */
#define REG08_RAM_Rd_1C (volatile UCHAR *)(REG_BASE + 0x6C) /* RAM Read 1C */
#define REG08_RAM_Rd_1D (volatile UCHAR *)(REG_BASE + 0x6D) /* RAM Read 1D */
#define REG08_RAM_Rd_1E (volatile UCHAR *)(REG_BASE + 0x6E) /* RAM Read 1E */
#define REG08_RAM_Rd_1F (volatile UCHAR *)(REG_BASE + 0x6F) /* RAM Read 1F */
#define REG08_DMA0_Config (volatile UCHAR *)(REG_BASE + 0x71) /* DMA0 Configuration */
#define REG08_DMA0_Control (volatile UCHAR *)(REG_BASE + 0x72) /* DMA0 Control */
#define REG08_DMA0_Remain_H (volatile UCHAR *)(REG_BASE + 0x74) /* DMA0 FIFO Remain High */
#define REG08_DMA0_Remain_L (volatile UCHAR *)(REG_BASE + 0x75) /* DMA0 FIFO Remain Low */
#define REG08_DMA0_Count_HH (volatile UCHAR *)(REG_BASE + 0x78) /* DMA0 Transfer Byte Counter High/High */
#define REG08_DMA0_Count_HL (volatile UCHAR *)(REG_BASE + 0x79) /* DMA0 Transfer Byte Counter High/Low */
#define REG08_DMA0_Count_LH (volatile UCHAR *)(REG_BASE + 0x7A) /* DMA0 Transfer Byte Counter Low/High */
#define REG08_DMA0_Count_LL (volatile UCHAR *)(REG_BASE + 0x7B) /* DMA0 Transfer Byte Counter Low/Low */
#define REG08_DMA0_RdData_0 (volatile UCHAR *)(REG_BASE + 0x7C) /* DMA0 Read Data High */
#define REG08_DMA0_RdData_1 (volatile UCHAR *)(REG_BASE + 0x7D) /* DMA0 Read Data Low */
#define REG08_DMA0_WrData_0 (volatile UCHAR *)(REG_BASE + 0x7E) /* DMA0 Write Data High */
#define REG08_DMA0_WrData_1 (volatile UCHAR *)(REG_BASE + 0x7F) /* DMA0 Write Data Low */
#define REG08_DMA1_Config (volatile UCHAR *)(REG_BASE + 0x81) /* DMA0 Configuration */
#define REG08_DMA1_Control (volatile UCHAR *)(REG_BASE + 0x82) /* DMA0 Control */
#define REG08_DMA1_Remain_H (volatile UCHAR *)(REG_BASE + 0x84) /* DMA0 FIFO Remain High */
#define REG08_DMA1_Remain_L (volatile UCHAR *)(REG_BASE + 0x85) /* DMA0 FIFO Remain Low */
#define REG08_DMA1_Count_HH (volatile UCHAR *)(REG_BASE + 0x88) /* DMA0 Transfer Byte Counter High/High */
#define REG08_DMA1_Count_HL (volatile UCHAR *)(REG_BASE + 0x89) /* DMA0 Transfer Byte Counter High/Low */
#define REG08_DMA1_Count_LH (volatile UCHAR *)(REG_BASE + 0x8A) /* DMA0 Transfer Byte Counter Low/High */
#define REG08_DMA1_Count_LL (volatile UCHAR *)(REG_BASE + 0x8B) /* DMA0 Transfer Byte Counter Low/Low */
#define REG08_DMA1_RdData_0 (volatile UCHAR *)(REG_BASE + 0x8C) /* DMA0 Read Data High */
#define REG08_DMA1_RdData_1 (volatile UCHAR *)(REG_BASE + 0x8D) /* DMA0 Read Data Low */
#define REG08_DMA1_WrData_0 (volatile UCHAR *)(REG_BASE + 0x8E) /* DMA0 Write Data High */
#define REG08_DMA1_WrData_1 (volatile UCHAR *)(REG_BASE + 0x8F) /* DMA0 Write Data Low */
#define REG08_IDE_Status (volatile UCHAR *)(REG_BASE + 0x90) /* IDE Status */
#define REG08_IDE_Control (volatile UCHAR *)(REG_BASE + 0x91) /* IDE Control */
#define REG08_IDE_Config_0 (volatile UCHAR *)(REG_BASE + 0x92) /* IDE Configuration 0 */
#define REG08_IDE_Config_1 (volatile UCHAR *)(REG_BASE + 0x93) /* IDE Configuration 1 */
#define REG08_IDE_Rmod (volatile UCHAR *)(REG_BASE + 0x94) /* IDE Register Mode */
#define REG08_IDE_Tmod (volatile UCHAR *)(REG_BASE + 0x95) /* IDE Transfer Mode */
#define REG08_IDE_Umod (volatile UCHAR *)(REG_BASE + 0x96) /* IDE Ultra-DMA Transfer Mode */
#define REG08_IDE_CRC_H (volatile UCHAR *)(REG_BASE + 0x9A) /* IDE CRC High */
#define REG08_IDE_CRC_L (volatile UCHAR *)(REG_BASE + 0x9B) /* IDE CRC Low */
#define REG08_IDE_Count_H (volatile UCHAR *)(REG_BASE + 0x9D) /* IDE Transfer Byte Counter High */
#define REG08_IDE_Count_M (volatile UCHAR *)(REG_BASE + 0x9E) /* IDE Transfer Byte Counter Middle */
#define REG08_IDE_Count_L (volatile UCHAR *)(REG_BASE + 0x9F) /* IDE Transfer Byte Counter Low */
#define REG08_IDE_RegAdrs (volatile UCHAR *)(REG_BASE + 0xA0) /* IDE Register Address */
#define REG08_IDE_RdRegValue_0 (volatile UCHAR *)(REG_BASE + 0xA2) /* IDE Register Read Value High */
#define REG08_IDE_RdRegValue_1 (volatile UCHAR *)(REG_BASE + 0xA3) /* IDE Register Read Value Low */
#define REG08_IDE_WrRegValue_0 (volatile UCHAR *)(REG_BASE + 0xA4) /* IDE Register Write Value High */
#define REG08_IDE_WrRegValue_1 (volatile UCHAR *)(REG_BASE + 0xA5) /* IDE Register Write Value Low */
#define REG08_IDE_SeqWrRegControl (volatile UCHAR *)(REG_BASE + 0xA6) /* IDE Sequential Register Write Control */
#define REG08_IDE_SeqWrRegCnt (volatile UCHAR *)(REG_BASE + 0xA7) /* IDE Sequential Register Write Counter */
#define REG08_IDE_SeqWrRegAdrs (volatile UCHAR *)(REG_BASE + 0xA8) /* IDE Sequential Register Write Address FIFO */
#define REG08_IDE_SeqWrRegValue (volatile UCHAR *)(REG_BASE + 0xA9) /* IDE Sequential Register Write Value FIFO */
#define REG08_IDE_RegConfig (volatile UCHAR *)(REG_BASE + 0xAC) /* IDE Register Configuration */
#define REG08_HostDeviceSel (volatile UCHAR *)(REG_BASE + 0xB1) /* Host Device Select */
#define REG08_ModeProtect (volatile UCHAR *)(REG_BASE + 0xB3) /* Mode Protection */
#define REG08_ClkSelect (volatile UCHAR *)(REG_BASE + 0xB5) /* Clock Select */
#define REG08_ChipConfig (volatile UCHAR *)(REG_BASE + 0xB7) /* Chip Configuration */
#define REG08_CPU_ChgEndian (volatile UCHAR *)(REG_BASE + 0xB9) /* Address for reading and do nothing*/
/*-------------------/
Block for individual Device /
/-------------------*/
#define REG08_D_SIE_IntStat (volatile UCHAR *)(REG_BASE + 0xE0) /* Device SIE Interrupt Status */
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