📄 newreg72v05.h
字号:
#define REG08_DMA1_Config (volatile UCHAR *)(REG_BASE + 0x81) /* DMA0 Configuration */
#define REG08_DMA1_Control (volatile UCHAR *)(REG_BASE + 0x82) /* DMA0 Control */
#define REG08_DMA1_Remain_H (volatile UCHAR *)(REG_BASE + 0x85) /* DMA0 FIFO Remain High */
#define REG08_DMA1_Remain_L (volatile UCHAR *)(REG_BASE + 0x84) /* DMA0 FIFO Remain Low */
#define REG08_DMA1_Count_HH (volatile UCHAR *)(REG_BASE + 0x89) /* DMA0 Transfer Byte Counter High/High */
#define REG08_DMA1_Count_HL (volatile UCHAR *)(REG_BASE + 0x88) /* DMA0 Transfer Byte Counter High/Low */
#define REG08_DMA1_Count_LH (volatile UCHAR *)(REG_BASE + 0x8B) /* DMA0 Transfer Byte Counter Low/High */
#define REG08_DMA1_Count_LL (volatile UCHAR *)(REG_BASE + 0x8A) /* DMA0 Transfer Byte Counter Low/Low */
#define REG08_DMA1_RdData_0 (volatile UCHAR *)(REG_BASE + 0x8C) /* DMA0 Read Data 0 */
#define REG08_DMA1_RdData_1 (volatile UCHAR *)(REG_BASE + 0x8D) /* DMA0 Read Data 1 */
#define REG08_DMA1_WrData_0 (volatile UCHAR *)(REG_BASE + 0x8E) /* DMA0 Write Data 0 */
#define REG08_DMA1_WrData_1 (volatile UCHAR *)(REG_BASE + 0x8F) /* DMA0 Write Data 1 */
#define REG08_IDE_Status (volatile UCHAR *)(REG_BASE + 0x90) /* IDE Status */
#define REG08_IDE_Control (volatile UCHAR *)(REG_BASE + 0x91) /* IDE Control */
#define REG08_IDE_Config_0 (volatile UCHAR *)(REG_BASE + 0x92) /* IDE Configuration 0 */
#define REG08_IDE_Config_1 (volatile UCHAR *)(REG_BASE + 0x93) /* IDE Configuration 1 */
#define REG08_IDE_Rmod (volatile UCHAR *)(REG_BASE + 0x94) /* IDE Register Mode */
#define REG08_IDE_Tmod (volatile UCHAR *)(REG_BASE + 0x95) /* IDE Transfer Mode */
#define REG08_IDE_Umod (volatile UCHAR *)(REG_BASE + 0x96) /* IDE Ultra-DMA Transfer Mode */
#define REG08_IDE_CRC_H (volatile UCHAR *)(REG_BASE + 0x9B) /* IDE CRC High */
#define REG08_IDE_CRC_L (volatile UCHAR *)(REG_BASE + 0x9A) /* IDE CRC Low */
#define REG08_IDE_Count_H (volatile UCHAR *)(REG_BASE + 0x9C) /* IDE Transfer Byte Counter High */
#define REG08_IDE_Count_M (volatile UCHAR *)(REG_BASE + 0x9F) /* IDE Transfer Byte Counter Middle */
#define REG08_IDE_Count_L (volatile UCHAR *)(REG_BASE + 0x9E) /* IDE Transfer Byte Counter Low */
#define REG08_IDE_RegAdrs (volatile UCHAR *)(REG_BASE + 0xA0) /* IDE Register Address */
#define REG08_IDE_RdRegValue_0 (volatile UCHAR *)(REG_BASE + 0xA2) /* IDE Register Read Value 0 */
#define REG08_IDE_RdRegValue_1 (volatile UCHAR *)(REG_BASE + 0xA3) /* IDE Register Read Value 1 */
#define REG08_IDE_WrRegValue_0 (volatile UCHAR *)(REG_BASE + 0xA4) /* IDE Register Write Value 0 */
#define REG08_IDE_WrRegValue_1 (volatile UCHAR *)(REG_BASE + 0xA5) /* IDE Register Write Value 1 */
#define REG08_IDE_SeqWrRegControl (volatile UCHAR *)(REG_BASE + 0xA6) /* IDE Sequential Register Write Control */
#define REG08_IDE_SeqWrRegCnt (volatile UCHAR *)(REG_BASE + 0xA7) /* IDE Sequential Register Write Counter */
#define REG08_IDE_SeqWrRegAdrs (volatile UCHAR *)(REG_BASE + 0xA8) /* IDE Sequential Register Write Address FIFO */
#define REG08_IDE_SeqWrRegValue (volatile UCHAR *)(REG_BASE + 0xA9) /* IDE Sequential Register Write Value FIFO */
#define REG08_IDE_RegConfig (volatile UCHAR *)(REG_BASE + 0xAC) /* IDE Register Configuration */
#define REG08_HostDeviceSel (volatile UCHAR *)(REG_BASE + 0xB1) /* Host Device Select */
#define REG08_ModeProtect (volatile UCHAR *)(REG_BASE + 0xB3) /* Mode Protection */
#define REG08_ClkSelect (volatile UCHAR *)(REG_BASE + 0xB5) /* Clock Select */
#define REG08_ChipConfig (volatile UCHAR *)(REG_BASE + 0xB7) /* Chip Configuration */
#define REG08_CPU_ChgEndian (volatile UCHAR *)(REG_BASE + 0xB9) /* Address for reading and do nothing*/
/*-------------------/
Block for individual Device /
/-------------------*/
#define REG08_D_SIE_IntStat (volatile UCHAR *)(REG_BASE + 0xE0) /* Device SIE Interrupt Status */
#define REG08_D_FIFO_IntStat (volatile UCHAR *)(REG_BASE + 0xE2) /* Device FIFO Interrupt Status */
#define REG08_D_BulkIntStat (volatile UCHAR *)(REG_BASE + 0xE3) /* Device Bulk Interrupt Status */
#define REG08_D_EPrIntStat (volatile UCHAR *)(REG_BASE + 0xE4) /* Device EPr Interrupt Status */
#define REG08_D_EP0IntStat (volatile UCHAR *)(REG_BASE + 0xE5) /* Device EP0 Interrupt Status */
#define REG08_D_EPaIntStat (volatile UCHAR *)(REG_BASE + 0xE6) /* Device EPa Interrupt Status */
#define REG08_D_EPbIntStat (volatile UCHAR *)(REG_BASE + 0xE7) /* Device EPb Interrupt Status */
#define REG08_D_EPcIntStat (volatile UCHAR *)(REG_BASE + 0xE8) /* Device EPc Interrupt Status */
#define REG08_D_SIE_IntEnb (volatile UCHAR *)(REG_BASE + 0xF0) /* Device SIE Interrupt Enable */
#define REG08_D_FIFO_IntEnb (volatile UCHAR *)(REG_BASE + 0xF2) /* Device FIFO Interrupt Enable */
#define REG08_D_BulkIntEnb (volatile UCHAR *)(REG_BASE + 0xF3) /* Device Bulk Interrupt Enable */
#define REG08_D_EPrIntEnb (volatile UCHAR *)(REG_BASE + 0xF4) /* Device EPr Interrupt Enable */
#define REG08_D_EP0IntEnb (volatile UCHAR *)(REG_BASE + 0xF5) /* Device EP0 Interrupt Enable */
#define REG08_D_EPaIntEnb (volatile UCHAR *)(REG_BASE + 0xF6) /* Device EPa Interrupt Enable */
#define REG08_D_EPbIntEnb (volatile UCHAR *)(REG_BASE + 0xF7) /* Device EPb Interrupt Enable */
#define REG08_D_EPcIntEnb (volatile UCHAR *)(REG_BASE + 0xF8) /* Device EPc Interrupt Enable */
#define REG08_D_Reset (volatile UCHAR *)(REG_BASE + 0x100) /* Device Reset */
#define REG08_D_NegoControl (volatile UCHAR *)(REG_BASE + 0x102) /* Device Negotiation Control */
#define REG08_D_ClrAllEPnJoin (volatile UCHAR *)(REG_BASE + 0x104) /* Device Clear All EPn Join */
#define REG08_D_XcvrControl (volatile UCHAR *)(REG_BASE + 0x105) /* Device Xcvr Control */
#define REG08_D_USB_Test (volatile UCHAR *)(REG_BASE + 0x106) /* Device USB Test */
#define REG08_D_EPnControl (volatile UCHAR *)(REG_BASE + 0x108) /* Device EPn Control */
#define REG08_D_EPrFIFO_Clr (volatile UCHAR *)(REG_BASE + 0x109) /* Device EPr FIFO Clear */
#define REG08_D_BulkOnlyControl (volatile UCHAR *)(REG_BASE + 0x10A) /* Device BulkOnly Control */
#define REG08_D_BulkOnlyConfig (volatile UCHAR *)(REG_BASE + 0x10B) /* Device BulkOnly Config */
#define REG08_D_EP0SETUP_0 (volatile UCHAR *)(REG_BASE + 0x110) /* Device EP0 SETUP 0 */
#define REG08_D_EP0SETUP_1 (volatile UCHAR *)(REG_BASE + 0x111) /* Device EP0 SETUP 1 */
#define REG08_D_EP0SETUP_2 (volatile UCHAR *)(REG_BASE + 0x112) /* Device EP0 SETUP 2 */
#define REG08_D_EP0SETUP_3 (volatile UCHAR *)(REG_BASE + 0x113) /* Device EP0 SETUP 3 */
#define REG08_D_EP0SETUP_4 (volatile UCHAR *)(REG_BASE + 0x114) /* Device EP0 SETUP 4 */
#define REG08_D_EP0SETUP_5 (volatile UCHAR *)(REG_BASE + 0x115) /* Device EP0 SETUP 5 */
#define REG08_D_EP0SETUP_6 (volatile UCHAR *)(REG_BASE + 0x116) /* Device EP0 SETUP 6 */
#define REG08_D_EP0SETUP_7 (volatile UCHAR *)(REG_BASE + 0x117) /* Device EP0 SETUP 7 */
#define REG08_D_USB_Address (volatile UCHAR *)(REG_BASE + 0x118) /* Device USB Address */
#define REG08_D_SETUP_Control (volatile UCHAR *)(REG_BASE + 0x11A) /* Device SETUP Control */
#define REG08_D_FrameNumber_H (volatile UCHAR *)(REG_BASE + 0x11F) /* Device FrameNumber High */
#define REG08_D_FrameNumber_L (volatile UCHAR *)(REG_BASE + 0x11E) /* Device FrameNumber Low */
#define REG08_D_EP0MaxSize (volatile UCHAR *)(REG_BASE + 0x120) /* Device EP0 Max Packet Size */
#define REG08_D_EP0Control (volatile UCHAR *)(REG_BASE + 0x121) /* Device EP0 Control */
#define REG08_D_EP0ControlIN (volatile UCHAR *)(REG_BASE + 0x122) /* Device EP0 Control IN */
#define REG08_D_EP0ControlOUT (volatile UCHAR *)(REG_BASE + 0x123) /* Device EP0 Control OUT */
#define REG08_D_EP0Join (volatile UCHAR *)(REG_BASE + 0x125) /* Device EP0 Join */
#define REG08_D_EPaMaxSize_H (volatile UCHAR *)(REG_BASE + 0x131) /* Device EPa Max Packet Size Low */
#define REG08_D_EPaMaxSize_L (volatile UCHAR *)(REG_BASE + 0x130) /* Device EPa Max Packet Size Low */
#define REG08_D_EPaConfig_0 (volatile UCHAR *)(REG_BASE + 0x132) /* Device EPa Configuration 0 */
#define REG08_D_EPaControl (volatile UCHAR *)(REG_BASE + 0x134) /* Device EPa Control */
#define REG08_D_EPaJoin (volatile UCHAR *)(REG_BASE + 0x135) /* Device EPa Join */
#define REG08_D_EPbMaxSize_H (volatile UCHAR *)(REG_BASE + 0x141) /* Device EPb Max Packet Size High */
#define REG08_D_EPbMaxSize_L (volatile UCHAR *)(REG_BASE + 0x140) /* Device EPb Max Packet Size Low */
#define REG08_D_EPbConfig_0 (volatile UCHAR *)(REG_BASE + 0x142) /* Device EPb Configuration 0 */
#define REG08_D_EPbControl (volatile UCHAR *)(REG_BASE + 0x144) /* Device EPb Control */
#define REG08_D_EPbJoin (volatile UCHAR *)(REG_BASE + 0x145) /* Device EPb Join */
#define REG08_D_EPcMaxSize_H (volatile UCHAR *)(REG_BASE + 0x151) /* Device EPc Max Packet Size High */
#define REG08_D_EPcMaxSize_L (volatile UCHAR *)(REG_BASE + 0x150) /* Device EPc Max Packet Size Low */
#define REG08_D_EPcConfig_0 (volatile UCHAR *)(REG_BASE + 0x152) /* Device EPc Configuration 0 */
#define REG08_D_EPcControl (volatile UCHAR *)(REG_BASE + 0x154) /* Device EPc Control */
#define REG08_D_EPcJoin (volatile UCHAR *)(REG_BASE + 0x155) /* Device EPc Join */
#define REG08_D_DescAdrs_H (volatile UCHAR *)(REG_BASE + 0x161) /* Device Descriptor Address High */
#define REG08_D_DescAdrs_L (volatile UCHAR *)(REG_BASE + 0x160) /* Device Descriptor Address Low */
#define REG08_D_DescSize_H (volatile UCHAR *)(REG_BASE + 0x163) /* Device Descriptor Size High */
#define REG08_D_DescSize_L (volatile UCHAR *)(REG_BASE + 0x162) /* Device Descriptor Size Low */
#define REG08_D_DMA0_FIFO_Control (volatile UCHAR *)(REG_BASE + 0x170) /* Device DMA0 FIFO Control */
#define REG08_D_DMA1_FIFO_Control (volatile UCHAR *)(REG_BASE + 0x172) /* Device DMA1 FIFO Control */
#define REG08_D_EPaStartAdrs_H (volatile UCHAR *)(REG_BASE + 0x185) /* Device EPa Start Address High */
#define REG08_D_EPaStartAdrs_L (volatile UCHAR *)(REG_BASE + 0x184) /* Device EPa Start Address Low */
#define REG08_D_EPbStartAdrs_H (volatile UCHAR *)(REG_BASE + 0x189) /* Device EPb Start Address High */
#define REG08_D_EPbStartAdrs_L (volatile UCHAR *)(REG_BASE + 0x188) /* Device EPb Start Address Low */
#define REG08_D_EPcStartAdrs_H (volatile UCHAR *)(REG_BASE + 0x18D) /* Device EPc Start Address High */
#define REG08_D_EPcStartAdrs_L (volatile UCHAR *)(REG_BASE + 0x18C) /* Device EPc Start Address Low */
#define REG08_D_EPcEndAdrs_H (volatile UCHAR *)(REG_BASE + 0x18F) /* Device EPc End Address High */
#define REG08_D_EPcEndAdrs_L (volatile UCHAR *)(REG_BASE + 0x18E) /* Device EPc End Address Low */
/*-----------------/
Block for individual Host /
/-----------------*/
#define REG08_H_SIE_IntStat_0 (volatile UCHAR *)(REG_BASE + 0xE0) /* Host SIE Interrupt Status 0 */
#define REG08_H_SIE_IntStat_1 (volatile UCHAR *)(REG_BASE + 0xE1) /* Host SIE Interrupt Status 1 */
#define REG08_H_FIFO_IntStat (volatile UCHAR *)(REG_BASE + 0xE2) /* Host FIFO Interrupt Status */
#define REG08_H_FrameIntStat (volatile UCHAR *)(REG_BASE + 0xE3) /* Host Frame Interrupt Status */
#define REG08_H_CHrIntStat (volatile UCHAR *)(REG_BASE + 0xE4) /* Host CHr Interrupt Status */
#define REG08_H_CH0IntStat (volatile UCHAR *)(REG_BASE + 0xE5) /* Host CH0 Interrupt Status */
#define REG08_H_CHaIntStat (volatile UCHAR *)(REG_BASE + 0xE6) /* Host CHa Interrupt Status */
#define REG08_H_CHbIntStat (volatile UCHAR *)(REG_BASE + 0xE7) /* Host CHb Interrupt Status */
#define REG08_H_CHcIntStat (volatile UCHAR *)(REG_BASE + 0xE8) /* Host CHc Interrupt Status */
#define REG08_H_CHdIntStat (volatile UCHAR *)(REG_BASE + 0xE9) /* Host CHd Interrupt Status */
#define REG08_H_CHeIntStat (volatile UCHAR *)(REG_BASE + 0xEA) /* Host CHe Interrupt Status */
#define REG08_H_SIE_IntEnb_0 (volatile UCHAR *)(REG_BASE + 0xF0) /* Host SIE Interrupt Enable 0 */
#define REG08_H_SIE_IntEnb_1 (volatile UCHAR *)(REG_BASE + 0xF1) /* Host SIE Interrupt Enable 1 */
#define REG08_H_FIFO_IntEnb (volatile UCHAR *)(REG_BASE + 0xF2) /* Host FIFO Interrupt Enable */
#define REG08_H_FrameIntEnb (volatile UCHAR *)(REG_BASE + 0xF3) /* Host Frame Interrupt Enable */
#define REG08_H_CHrIntEnb (volatile UCHAR *)(REG_BASE + 0xF4) /* Host CHr Interrupt Enable */
#define REG08_H_CH0IntEnb (volatile UCHAR *)(REG_BASE + 0xF5) /* Host CH0 Interrupt Enable */
#define REG08_H_CHaIntEnb (volatile UCHAR *)(REG_BASE + 0xF6) /* Host CHa Interrupt Enable */
#define REG08_H_CHbIntEnb (volatile UCHAR *)(REG_BASE + 0xF7) /* Host CHb Interrupt Enable */
#define REG08_H_CHcIntEnb (volatile UCHAR *)(REG_BASE + 0xF8) /* Host CHc Interrupt Enable */
#define REG08_H_CHdIntEnb (volatile UCHAR *)(REG_BASE + 0xF9) /* Host CHd Interrupt Enable */
#define REG08_H_CHeIntEnb (volatile UCHAR *)(REG_BASE + 0xFA) /* Host CHe Interrupt Enable */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -