📄 usbd_sampletask.c
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memset( &XferInfo, 0, sizeof( DEVICE_TASK_XFER_INFO ));
XferInfo.mode = DEVICE_TASK_XFER_MODE_DMA; // DMA transfer
XferInfo.size = WRBUFF_SIZE; // Number of data transfer
XferInfo.dir = DEVICE_TASK_XFER_DIR_OUT; // Direction of data transfer
XferInfo.pAddress = NULL;
XferInfo.dmaChannel = DEVICE_TASK_DMA_CH0; // DMA channel
// Execute ATA command
result = DEVICE_TASK_ExecIdeCmd( LUN0, DEVICE_TASK_IDECMD_TYPE_ATA, &AtaCmd, &XferInfo );
if ( result != DEVICE_TASK_STATUS_SUCCESS )
{
// Failed to execute ATA command
return STATUS_UNSUCCESSFUL;
}
// Wait until preparation of DMA transfer completed
while( TskInfo.DMAxferFlg != DMA_READY )
{
dly_tsk( 100 );
}
#ifdef TOYA2_C
// Set register of source address for DMA Ch0
rlMX21_SAR0 = (unsigned long)pWrBuff;
// Set register of destination address for DMA Ch0
rlMX21_DAR0 = WRITEDEVICEADR ;
// Set register of transfer count for DMA Ch0
rlMX21_CNTR0 = WRBUFF_SIZE;
rlMX21_BLR0 = 16;
// Set register of control for DMA Ch0
rlMX21_CCR0 =
(0<<14) | /* ACRPT : 0 or 1 :Auto Clear Off */
(2<<12) | /* DMOD : 0 - 3 :Dst FIFO */
(0<<10) | /* SMOD : 0 - 3 :Src Linear Mem */
(0<< 9) | /* MDIR : 0 or 1 :Direction: Inc */
(0<< 8) | /* MSEL : 0 or 1 :N/A */
(2<< 6) | /* DSIZ : 0 - 3 :dst 16bit Port */
(0<< 4) | /* SSIZ : 0 - 3 :src 32bit Port */
(1<< 3) | /* REN : 0 or 1 :Request Enable */
(0<< 2) | /* RPT : 0 or 1 :Repeat Disable */
(0<< 1) | /* FRC : 0 or 1 :Force DMA Non */
(1<< 0) ; /* CEN : 0 or 1 :Enable DMA Ch */
// Send request to start DMA transfer
result = DEVICE_TASK_StartDma();
if ( result != DEVICE_TASK_STATUS_SUCCESS )
{
// Failed for request to start DMA transfer
// Clear register of control for DMA Ch0
rlMX21_CCR0 = 0;
rlMX21_DISR |= 1;
return STATUS_UNSUCCESSFUL;
}
LED_Off(8);
LED_Off(7);
LED_Off(6);
LED_Off(5);
LED_On(8);
// Wait until DMA transfer completed
while(( TskInfo.DMAxferFlg != DMA_XFERCMP ) &&
!(rlMX21_DISR & 0x01) )
{
dly_tsk( 100 );
}
LED_On(7);
// Wait notification of completion of IDE command sequence
while( TskInfo.IDEcmdCmpFlg == IDE_CMDSEQ_RDY )
{
dly_tsk( 100 );
}
LED_On(6);
if( TskInfo.IDEcmdCmpFlg != IDE_CMDSEQ_CMP )
{
rlMX21_CCR0 = 0;
rlMX21_DISR |= 1;
return STATUS_UNSUCCESSFUL;
}
LED_On(5);
// Clear register of control for DMA Ch0
rlMX21_CCR0 = 0;
rlMX21_DISR |= 1;
#else
// Set register of source address for DMA Ch0
sfr_outl( DMA_CH0SRCADD, (unsigned long)pWrBuff );
// Set register of destination address for DMA Ch0
sfr_outl( DMA_CH0DSTADD, DEVICEADR );
// Set register of transfer count for DMA Ch0
sfr_outl( DMA_CH0TRCNT, WRBUFF_SIZE/2 );
// Set register of control for DMA Ch0
sfr_outl( DMA_CH0CTRL, (DMACH_ACKMODE | DMACH_SRCADD_INC |
DMACH_TRSIZE_16BIT | DMACH_CHANNELEN));
// Send request to start DMA transfer
result = DEVICE_TASK_StartDma();
if ( result != DEVICE_TASK_STATUS_SUCCESS )
{
// Failed for request to start DMA transfer
// Clear register of control for DMA Ch0
sfr_outl( DMA_CH0CTRL, 0 );
return STATUS_UNSUCCESSFUL;
}
// Wait until DMA transfer completed
while(( TskInfo.DMAxferFlg != DMA_XFERCMP ) &&
!( sfr_inl( DMA_CH0CTRL ) & DMACH_TREND ) )
{
dly_tsk( 100 );
}
// Wait notification of completion of IDE command sequence
while( TskInfo.IDEcmdCmpFlg == IDE_CMDSEQ_RDY )
{
dly_tsk( 100 );
}
if( TskInfo.IDEcmdCmpFlg != IDE_CMDSEQ_CMP )
{
sfr_outl( DMA_CH0CTRL, 0 );
return STATUS_UNSUCCESSFUL;
}
// Clear register of control for DMA Ch0
sfr_outl( DMA_CH0CTRL, 0 );
#endif
return STATUS_SUCCESS;
}
#endif
/*
//=============================================================================
// Function_Name: ATA_ReadCmdAsync
// description : Send ATA Read command(Asynchronous mode)
// argument :
// return :
// flag :
// global :
//=============================================================================
*/
#ifdef CMD_ASYNC_MODE
long ATA_ReadCmdAsync( void )
{
long result;
TskInfo.DMAxferFlg = DMA_NOTREADY;
TskInfo.IDEcmdCmpFlg = IDE_CMDSEQ_RDY;
#ifdef BIG_DRIVE
// Create ATA command(BIG DRIVE READ[25h])
memset( &AtaCmd, 0, sizeof( DEVICE_TASK_ATA_CMD ));
AtaCmd.features = 0; // Features
AtaCmd.secCnt = 0x02;
AtaCmd.bicSecCnt = 0x00; // Bic Drive Sector count
AtaCmd.bicSecNum = 0; // Bic Drive Sector countLBA[7:0]
AtaCmd.bicCylLow = 0; // Bic Drive Sector countLBA[15:8]
AtaCmd.bicCylHigh = 0; // Bic Drive Sector countLBA[23:16]
AtaCmd.bicDevHead = 0x01; // Bic Drive Sector countDevice/Head,LBA[27:24]
AtaCmd.command = 0x25; // Command
#else
// Create ATA command(READ DMA[C8h])
memset( &AtaCmd, 0, sizeof( DEVICE_TASK_ATA_CMD ));
AtaCmd.features = 0; // Features
AtaCmd.secCnt = (unsigned char)(SECTOR_CNT); // Sector count
AtaCmd.secNum = 0; // LBA[7:0]
AtaCmd.cylLow = 0; // LBA[15:8]
AtaCmd.cylHigh = 0; // LBA[23:16]
AtaCmd.devHead = 0x00; // Device/Head,LBA[27:24]
AtaCmd.command = ATA_READ_DMA; // Command
#endif
// Set information for data transfer
memset( &XferInfo, 0, sizeof( DEVICE_TASK_XFER_INFO ));
XferInfo.mode = DEVICE_TASK_XFER_MODE_DMA; // DMA transfer
XferInfo.size = RDBUFF_SIZE; // Number of data transfer
XferInfo.dir = DEVICE_TASK_XFER_DIR_IN; // Direction of data transfer
XferInfo.pAddress = NULL;
XferInfo.dmaChannel = DEVICE_TASK_DMA_CH0; // DMA channel
#ifdef TOYA2_C
// Execute ATA command
result = DEVICE_TASK_ExecIdeCmd( LUN0, DEVICE_TASK_IDECMD_TYPE_ATA, &AtaCmd, &XferInfo );
if ( result != DEVICE_TASK_STATUS_SUCCESS )
{
// Failed to execute ATA command
// Clear register of control for DMA Ch0
rlMX21_DISR |= 1;
rlMX21_CCR0 = 0;
return STATUS_UNSUCCESSFUL;
}
// Wait until preparation of DMA transfer completed
while( TskInfo.DMAxferFlg != DMA_READY )
{
dly_tsk( 100 );
}
// Set register of source address for DMA Ch0
rlMX21_SAR0 = READDEVICEADR;
// Set register of destination address for DMA Ch0
rlMX21_DAR0 = (unsigned long )pRdBuff ;
// Set register of transfer count for DMA Ch0
rlMX21_CNTR0 = RDBUFF_SIZE;
rlMX21_BLR0 = 16;
/* Flush and clear data cache */
flush_Dcache((unsigned long)pRdBuff, WRBUFF_SIZE);
clean_Dcache((unsigned long)pRdBuff, WRBUFF_SIZE);
// Set register of control for DMA Ch0
rlMX21_CCR0 =
(0<<14) | /* ACRPT : 0 or 1 :Auto Clear Off */
(0<<12) | /* DMOD : 0 - 3 :Dst Linear Mem */
(2<<10) | /* SMOD : 0 - 3 :Src FIFO */
(0<< 9) | /* MDIR : 0 or 1 :Direction: Inc */
(0<< 8) | /* MSEL : 0 or 1 :N/A */
(0<< 6) | /* DSIZ : 0 - 3 :dst 32bit Port */
(2<< 4) | /* SSIZ : 0 - 3 :src 16bit Port */
(1<< 3) | /* REN : 0 or 1 :Request Enable */
(0<< 2) | /* RPT : 0 or 1 :Repeat Disable */
(0<< 1) | /* FRC : 0 or 1 :Force DMA Non */
(1<< 0) ; /* CEN : 0 or 1 :Enable DMA Ch */
LED_Off(4);
LED_Off(3);
LED_Off(2);
LED_Off(1);
// Send request to start DMA transfer
result = DEVICE_TASK_StartDma();
if ( result != DEVICE_TASK_STATUS_SUCCESS )
{
// Failed for request to start DMA transfer
// Clear register of control for DMA Ch0
rlMX21_CCR0 = 0;
rlMX21_DISR |= 1;
return STATUS_UNSUCCESSFUL;
}
LED_On(4);
// Wait until DMA transfer completed
while(( TskInfo.DMAxferFlg != DMA_XFERCMP ) &&
!(rlMX21_DISR & 0x01) )
{
dly_tsk( 100 );
}
LED_On(3);
// Wait notification of completion of IDE command sequence
while( TskInfo.IDEcmdCmpFlg == IDE_CMDSEQ_RDY )
{
dly_tsk( 100 );
}
LED_On(2);
if( TskInfo.IDEcmdCmpFlg != IDE_CMDSEQ_CMP )
{
rlMX21_CCR0 = 0;
rlMX21_DISR |= 1;
return STATUS_UNSUCCESSFUL;
}
LED_On(1);
// Clear register of control for DMA Ch0
rlMX21_CCR0 = 0;
rlMX21_DISR |= 1;
#else
// Execute ATA command
result = DEVICE_TASK_ExecIdeCmd( LUN0, DEVICE_TASK_IDECMD_TYPE_ATA, &AtaCmd, &XferInfo );
if ( result != DEVICE_TASK_STATUS_SUCCESS )
{
// Failed to execute ATA command
// Clear register of control for DMA Ch0
sfr_outl( DMA_CH0CTRL, 0 );
return STATUS_UNSUCCESSFUL;
}
// Wait until preparation of DMA transfer completed
while( TskInfo.DMAxferFlg != DMA_READY )
{
dly_tsk( 100 );
}
// Set register of source address for DMA Ch0
sfr_outl( DMA_CH0SRCADD, DEVICEADR );
// Set register of destination address for DMA Ch0
sfr_outl( DMA_CH0DSTADD, (unsigned long )pRdBuff );
// Set register of transfer count for DMA Ch0
sfr_outl( DMA_CH0TRCNT, RDBUFF_SIZE/2 );
// Set register of control for DMA Ch0
sfr_outl( DMA_CH0CTRL, (DMACH_DESTADD_INC |
DMACH_TRSIZE_16BIT | DMACH_CHANNELEN));
// Send request to start DMA transfer
result = DEVICE_TASK_StartDma();
if ( result != DEVICE_TASK_STATUS_SUCCESS )
{
// Failed for request to start DMA transfer
// Clear register of control for DMA Ch0
sfr_outl( DMA_CH0CTRL, 0 );
return STATUS_UNSUCCESSFUL;
}
// Wait until DMA transfer completed
while(( TskInfo.DMAxferFlg != DMA_XFERCMP ) &&
!( sfr_inl( DMA_CH0CTRL ) & DMACH_TREND ) )
{
dly_tsk( 100 );
}
// Wait notification of completion of IDE command sequence
while( TskInfo.IDEcmdCmpFlg == IDE_CMDSEQ_RDY )
{
dly_tsk( 100 );
}
if( TskInfo.IDEcmdCmpFlg != IDE_CMDSEQ_CMP )
{
sfr_outl( DMA_CH0CTRL, 0 );
return STATUS_UNSUCCESSFUL;
}
// Clear register of control for DMA Ch0
sfr_outl( DMA_CH0CTRL, 0 );
#endif
return STATUS_SUCCESS;
}
#endif
/*
//=============================================================================
// Function_Name: ATA_WriteCmdSync
// description : Send ATA Write command(Synchronous mode)
// argument :
// return :
// flag :
// global :
//=============================================================================
*/
long ATA_WriteCmdSync( void )
{
long result;
#ifdef TOYA2_C
// Set register of source address for DMA Ch0
rlMX21_SAR0 = (unsigned long)pWrBuff;
// Set register of destination address for DMA Ch0
rlMX21_DAR0 = WRITEDEVICEADR ;
// Set register of transfer count for DMA Ch0
rlMX21_CNTR0 = WRBUFF_SIZE;
// Set register of control for DMA Ch0
rlMX21_CCR0 =
(0<<14) | /* ACRPT : 0 or 1 :Auto Clear Off */
(2<<12) | /* DMOD : 0 - 3 :Dst FIFO */
(0<<10) | /* SMOD : 0 - 3 :Src Linear Mem */
(0<< 9) | /* MDIR : 0 or 1 :Direction: Inc */
(0<< 8) | /* MSEL : 0 or 1 :N/A */
(2<< 6) | /* DSIZ : 0 - 3 :dst 16bit Port */
(0<< 4) | /* SSIZ : 0 - 3 :src 32bit Port */
(1<< 3) | /* REN : 0 or 1 :Request Enable */
(0<< 2) | /* RPT : 0 or 1 :Repeat Disable */
(0<< 1) | /* FRC : 0 or 1 :Force DMA Non */
(1<< 0) ; /* CEN : 0 or 1 :Enable DMA Ch */
#else
// Set register of source address for DMA Ch0
sfr_outl( DMA_CH0SRCADD, (unsigned long)pWrBuff );
// Set register of destination address for DMA Ch0
sfr_outl( DMA_CH0DSTADD, DEVICEADR );
// Set register of transfer count for DMA Ch0
sfr_outl( DMA_CH0TRCNT, WRBUFF_SIZE/2 );
// Set register of control for DMA Ch0
sfr_outl( DMA_CH0CTRL, (DMACH_ACKMODE | DMACH_SRCADD_INC |
DMACH_TRSIZE_16BIT | DMACH_CHANNELEN));
#endif
#ifdef BIG_DRIVE
// Create ATA command(BIG DRIVE WRITE [35h])
memset( &AtaCmd, 0, sizeof( DEVICE_TASK_ATA_CMD ));
AtaCmd.features = 0; // Features
AtaCmd.secCnt = 0x02;
AtaCmd.bicSecCnt = 0x00; // Bic Drive Sector count
AtaCmd.bicSecNum = 0; // Bic Drive Sector countLBA[7:0]
AtaCmd.bicCylLow = 0; // Bic Drive Sector countLBA[15:8]
AtaCmd.bicCylHigh = 0; // Bic Drive Sector countLBA[23:16]
AtaCmd.bicDevHead = 0x41; // Bic Drive Sector countDevice/Head,LBA[27:24]
AtaCmd.command = 0x35; // Command
#else
// Create ATA command(WRITE DMA[CAh])
memset( &AtaCmd, 0, sizeof( DEVICE_TASK_ATA_CMD ));
AtaCmd.features = 0; // Features
AtaCmd.secCnt = 0x02; // Sector count
AtaCmd.secNum = 0; // LBA[7:0]
AtaCmd.cylLow = 0; // LBA[15:8]
AtaCmd.cylHigh = 0; // LBA[23:16]
AtaCmd.devHead = 0x40; // Device/Head,LBA[27:24]
AtaCmd.command = 0xCA; // Command
#endif
// Set information for data transfer
memset( &XferInfo, 0, sizeof( DEVICE_TASK_XFER_INFO ));
XferInfo.mode = DEVICE_TASK_XFER_MODE_DMA; // DMA transfer
XferInfo.size = WRBUFF_SIZE; // Number of data transfer
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