📄 usbh_hcds_user_config.h
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/*
* description: USBH HCD User Configuration Definition
* Maker : Hiromichi Kondo
* Copyright : (C)2005,SEIKO EPSON Corp. All Rights Reserved.
*/
#ifndef USBH_HCD_USER_CONFIG_H
#define USBH_HCD_USER_CONFIG_H
#ifdef __cplusplus
extern "C" {
#endif /* cplusplus */
#include <OSCall.h>
/*****************************************
* Define definition
*****************************************/
#define USBH_HCD_OSC_WAKEUP_TIME (0xBBCC) /* Waiting time for OSC wake-up(2ms)*/
#define USBH_HCD_CHIP_INT_LEVEL (0) /* Logical level of xINT signal(0: Negative logic, 1: Positive logic) */
#define USBH_HCD_CHIP_INT_MODE (0) /* Output mode of xINT signal(0:1/0 mode,1:Hi-z/0 mode */
#define USBH_HCD_CHIP_DREQ_LEVEL (0) /* Logical level of xDREQ0 and 1(0: Negative logic, 1: Positive logic) */
#define USBH_HCD_CHIP_DACK_LEVEL (0) /* Logical level of xDACK0 and 1(0: Negative logic, 1: Positive logic) */
#define USBH_HCD_CHIP_CS_MODE (1) /* Operation mode of DMA0 and 1(0:Operate as an effective DMA access when xDACK0 and 1 are asserted */
/* 1:Effective DMA access when xCS, xDACK0, and 1 are asserted */
#ifdef LITTLE_ENDIAN_C
#define USBH_HCD_CHIP_CPU_ENDIAN (1) /* CPU bus at 16bit mode(0: even address as high-ranking side, 1:even address as high-ranking side */
#else
#define USBH_HCD_CHIP_CPU_SWAP (0) /* CPU bus at 16bit mode(0: even address as high-ranking side, 1:even address as high-ranking side */
#endif
#define USBH_HCD_CHIP_BUS_MODE (2) /* Operation mode of CPU(0:16bit Strobe mode, 1:8bit mode, 2:16bit BE mode) */
#define USBH_HCD_CHIP_ACT_IDE_TERM (0) /* Pull-up/pull-down setting of IO cell in IDE port(0: Connect, 1: Disconnect) */
#define USBH_HCD_CHIP_CLK_SELECT (1) /* Clock used with this LSI(0:12MHz,1:24MHz) */
#define USBH_HCD_CHIP_ACT_DD_TERM (0) /* Pull-up/pull-down setting of IO cell in IDE port(0: Connect, 1: Disconnect) */
#ifdef HOST_1PORT
#define USBH_HCD_CHIP_PORT1_X_2 (1) /* Host/Device is operated in 1 port (0:not used, 1: Use ) */
#else
#define USBH_HCD_CHIP_PORT1_X_2 (0) /* Host/Device is operated in 1 port (0: not used, 1: Use ) */
#endif
#define USBH_HCD_USED_DMA_FOR_IDE (1) /* Whether DMA of CPU I/F is used with IDE or not(0: not used, 1: Use ) */
#define USBH_HCD_USED_DMACH_FOR_IDE (1) /* Channel number(0 - 1) when DMA of CPU I/F is used with IDE */
#define USBH_HCD_DMA_MODE (1) /* DMA setting of CPU I/F and acknowledge mode value(0:Normal, 1:Address Decode Mode) */
#define USBH_HCD_DMA_REQ_ASSERT_COUNT (1) /* DMA setting of CPU I/F and ReqAssertCount value(0:Normal, 1:16Byte, 2:32Byte, 3:64Byte) */
#define USBH_HCD_URB_START_FRAME_DELAY (3) /* Number of delay frames from setting of URB's startFrame to execution of URB */
#define USBH_HCD_DIS_CHIRP_FINISH (0) /* Mode that continues detecting function even if becoming NG in Chirp detection (0:invalid, 1:valid) */
#define USBH_HCD_VBUS_ERR_CHECK_COUNT (3) /* Times of counter for judgment to avoid overcurrent at hot plug in VBU Err detection (0:invalid, 1:valid) */
#define CPUDMACH (0) /* CPU DMA channel number 0 */
#define CPUDMA_IRQ (32) /* IRQ 32 */
#define CPUTIMERCH (2) /* CPU Timer channel number 2 */
#define CPUTIMER_IRQ (27-CPUTIMERCH) /* IRQ 24 - 26 */
#define TIMER_1MS_COUNT (16*1024) /* 1ms in 16MHz */
/*****************************************
* Macro declaration
*****************************************/
Inline void USBH_HCDS_InterruptEnable( void )
{
if( OS_SnsCtx() != TRUE ){
OS_UnlCpu();
}
}
Inline void USBH_HCDS_InterruptDisable( void )
{
if( OS_SnsCtx() != TRUE ){
OS_LocCpu();
}
}
/*****************************************
* Function prototype declaration
*****************************************/
extern void USBH_HCDS_CPUDMAStart( unsigned char dir, void *pSrcAdrs, void *pDesAdrs,
unsigned long size, CALLBACK_PROC pfnCallback );
extern void USBH_HCDS_CPUDMAStop( void );
extern void USBH_HCDS_CPUTimerStart( CALLBACK_PROC pfnCallback );
extern void USBH_HCDS_CPUTimerStop( void );
#ifdef __cplusplus
}
#endif /* cplusplus */
#endif /* USBH_HCD_USER_CONFIG_H */
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