📄 usbh_hcds_72v05.c
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/*
* description : Host Contoller control part(static)
* Maker : Hiromichi Kondo
* Copyright : (C)2005,SEIKO EPSON Corp. All Rights Reserved.
*/
#include <string.h> /* memset */
#include <Reg72V05.h>
#include <usbh_hcd.h>
#include <usbh_hcds_common.h>
#include <usbh_hcds_user_config.h>
#include <usbh_hcds_port.h>
#include <usbh_hcds_72V05.h>
#include <SPRDEF.h>
#include <SPRSTS.h>
#include <OSCall.h>
/*****************************************
* Definition
*****************************************/
#define FIFO_START_ADRS_CBW USBH_HCDS_HC_FIFO_START_ADRS_CBW
#define FIFO_START_ADRS_CSW USBH_HCDS_HC_FIFO_START_ADRS_CSW
#define FIFO_START_ADRS_ALLOC USBH_HCDS_HC_FIFO_START_ADRS_ALLOC
#define FIFO_END_ADRS_ALLOC USBH_HCDS_HC_FIFO_END_ADRS_ALLOC
#define FIFO_SIZE_ALLOC USBH_HCDS_HC_FIFO_SIZE_ALLOC
#define FIFO_START_ADRS_CTRL USBH_HCDS_HC_FIFO_START_ADRS_CTRL
#define FIFO_SIZE_CTRL USBH_HCDS_HC_FIFO_SIZE_CTRL
#define FIFO_END_ADRS_CTRL USBH_HCDS_HC_FIFO_END_ADRS_CTRL
#define FIFO_START_ADRS_INT USBH_HCDS_HC_FIFO_START_ADRS_INT
#define FIFO_SIZE_INT USBH_HCDS_HC_FIFO_SIZE_INT
#define FIFO_END_ADRS_INT USBH_HCDS_HC_FIFO_END_ADRS_INT
#define FIFO_START_ADRS_ISO USBH_HCDS_HC_FIFO_START_ADRS_ISO
#define FIFO_SIZE_ISO USBH_HCDS_HC_FIFO_SIZE_ISO
#define FIFO_END_ADRS_ISO USBH_HCDS_HC_FIFO_END_ADRS_ISO
#define FIFO_START_ADRS_BULK USBH_HCDS_HC_FIFO_START_ADRS_BULK
#define FIFO_SIZE_BULK USBH_HCDS_HC_FIFO_SIZE_BULK
#define FIFO_END_ADRS_BULK USBH_HCDS_HC_FIFO_END_ADRS_BULK
#define FIFO_BLOCK_SIZE USBH_HCDS_HC_FIFO_BLOCK_SIZE
#define RAM_RD_BLOCK_SIZE (0x04)
#define RAM_RD_AREA_SIZE (0x20)
#define NUM_USB_CH USBH_HCDS_HC_NUM_USB_CH
#define NUM_CPU_DMA USBH_HCDS_HC_NUM_CPU_DMA
#define NUM_USB_CTRL_CH USBH_HCDS_HC_NUM_USB_CTRL_CH
#define NUM_USB_BULK_CH USBH_HCDS_HC_NUM_USB_BULK_CH
#define NUM_USB_INT_CH USBH_HCDS_HC_NUM_USB_INT_CH
#define NUM_USB_ISO_CH USBH_HCDS_HC_NUM_USB_ISO_CH
#define INDEX_USB_CTRL_CH USBH_HCDS_HC_INDEX_USB_CTRL_CH
#define INDEX_USB_BULK_CH USBH_HCDS_HC_INDEX_USB_BULK_CH
#define INDEX_USB_INT_CH USBH_HCDS_HC_INDEX_USB_INT_CH
#define INDEX_USB_ISO_CH USBH_HCDS_HC_INDEX_USB_ISO_CH
#define CH_TYPE_CTRL USBH_HCDS_HC_TYPE_CTRL
#define CH_TYPE_BULK USBH_HCDS_HC_TYPE_BULK
#define CH_TYPE_INT USBH_HCDS_HC_TYPE_INT
#define CH_TYPE_ISO USBH_HCDS_HC_TYPE_ISO
#define BIT15 (0x8000)
#define BIT14 (0x4000)
#define BIT13 (0x2000)
#define BIT12 (0x1000)
#define BIT11 (0x0800)
#define BIT10 (0x0400)
#define BIT9 (0x0200)
#define BIT8 (0x0100)
#define BIT7 (0x0080)
#define BIT6 (0x0040)
#define BIT5 (0x0020)
#define BIT4 (0x0010)
#define BIT3 (0x0008)
#define BIT2 (0x0004)
#define BIT1 (0x0002)
#define BIT0 (0x0001)
#define MASK_CPU_DMACH_0 (BIT1 | BIT0)
#define MASK_CPU_DMACH_1 (BIT3 | BIT2)
#define MASK_CPU_DMACH (NUM_CPU_DMA - 1)
#define MASK_1BIT (BIT0)
#define MASK_2BIT (BIT1 | BIT0)
#define REVISION_NUMBER (0x50)
#define CHIP_RESET (0xFFFF)
#define MODE_PROTECT_OFF (0x0056)
#define MASK_RD_REMAIN_VALID (BIT15)
#define TERM_SELECT_HS (0x00)
#define TERM_SELECT_FS (0x01)
#define XCVR_SELECT_HS (0x00)
#define XCVR_SELECT_FS (0x01)
#define XCVR_SELECT_LS (0x02)
#define OPMODE_NORMAL_OPERATION (0x00)
#define OPMODE_NON_DRIVING (0x01)
#define OPMODE_DIS_BITSTUFFING_NRZI (0x02)
#define OPMODE_POWER_DOWN (0x03)
#define NEGO_MODE_GO_IDLE (0x01)
#define NEGO_MODE_GO_WAIT_CONNECT (0x02)
#define NEGO_MODE_GO_DISABLED (0x03)
#define NEGO_MODE_GO_RESET (0x04)
#define NEGO_MODE_GO_OPERATIONAL (0x05)
#define NEGO_MODE_GO_SUSPEND (0x06)
#define NEGO_MODE_GO_RESUME (0x07)
#define NEGO_MODE_GO_WAIT_CONNECT_TO_DIS (0x09)
#define NEGO_MODE_GO_WAIT_CONNECT_TO_OP (0x0A)
#define NEGO_MODE_GO_RESET_TO_OP (0x0C)
#define NEGO_MODE_GO_SUSPEND_TO_OP (0x0E)
#define NEGO_MODE_GO_RESUME_TO_OP (0x0F)
#define NEGO_AUTO_MODE_CANCEL (0x80)
#define NEGO_STATE_IDLE (0x01)
#define NEGO_STATE_WAIT_CONNECT (0x02)
#define NEGO_STATE_DISABLED (0x03)
#define NEGO_STATE_RESET (0x04)
#define NEGO_STATE_OPERATIONAL (0x05)
#define NEGO_STATE_SUSPEND (0x06)
#define NEGO_STATE_RESUME (0x07)
#define NEGO_PORTSPEED_HIGH (0x00)
#define NEGO_PORTSPEED_FULL (0x01)
#define NEGO_PORTSPEED_LOW (0x03)
#define CLR_ALL_JOIN (0xFF)
#define TID_SETUP (0x00)
#define TID_OUT (0x01)
#define TID_IN (0x02)
#define CONDITION_CODE_NO_ERROR (0x00)
#define CONDITION_CODE_STALL (0x01)
#define CONDITION_CODE_DATA_OVER_RUN (0x02)
#define CONDITION_CODE_DATA_UNDER_RUN (0x03)
#define CONDITION_CODE_RETRY_ERROR (0x04)
#define INT_ALL_CLEAR (0xFF)
/* H_CHxIntStat */
#define INT_BO_SUPPORT_STOP (BIT0)
#define INT_BO_SUPPORT_CMP (BIT1)
#define INT_CTL_SUPPORT_STOP (BIT0)
#define INT_CTL_SUPPORT_CMP (BIT1)
#define INT_CHANGE_CONDITION (BIT4)
#define INT_TRAN_ERR (BIT5)
#define INT_TRAN_ACK (BIT6)
#define INT_TOTAL_SIZE_CMP (BIT7)
/* CPU_IntStat */
#define INT_RAM_RD_CMP (BIT7)
#define CTL_SUPPORT_STATE_IDLE (0x00)
#define CTL_SUPPORT_STATE_SETUP (0x01)
#define CTL_SUPPORT_STATE_DATA (0x02)
#define CTL_SUPPORT_STATE_STATUS (0x03)
#define BO_SUPPORT_STATE_IDLE (0x00)
#define BO_SUPPORT_STATE_CBW (0x01)
#define BO_SUPPORT_STATE_DATA (0x02)
#define BO_SUPPORT_STATE_CSW (0x03)
#define CHX_TRAN_GO (BIT0)
#define MASK_FRACTION (0x0001)
#define MASK_BM_REQUEST_TYPE_DIR (0x80)
#define BO_CBW_SIZE (31)
#define BO_CSW_SIZE (13)
#define MASK_EP_NUMBER (0x7F)
#define MASK_MICROFRAME_INTERVAL (0x07)
#define MASK_FRAME_NUMBER (0x07FF)
#define MAX_MICROFRAME_INTERVAL (0x0400)
#define WAIT_SOF_DELAY (2)
/*****************************************
*Structures Definition
*****************************************/
typedef struct tagHC_MANAGER{
CALLBACK_PROC pfnPMFinishedCallback;
CALLBACK_PROC pfnPortInterruptCallback;
CALLBACK_PROC pfnDetDevConCallback;
struct{
unsigned short chirpNG:1;
unsigned short usedDMAforIDE:1;
unsigned short disChirpOff:1;
unsigned short reserved:13;
}bmFlags;
unsigned char usedDMAChforCH[NUM_CPU_DMA];
unsigned char usedDMAChforIDE;
unsigned char vbusErrCount;
unsigned char vbusErrCalled;
unsigned char bmSOFCheck;
}HC_MANAGER;
typedef struct tagURB_INFO{
USBH_HCD_URB *psUrb;
CALLBACK_PROC pfnCallback;
unsigned char *pBufAdrs;
unsigned long reqDataSize;
unsigned long remainDataSize;
struct{
unsigned short usedDMA:1;
unsigned short dirOUT:1;
unsigned short shortNotOK:1;
unsigned short tranGo:1;
unsigned short supportBO:1;
unsigned short autoZeroPacket:1;
unsigned short tranErr:1;
unsigned short directCopy:1;
unsigned short reqDMA:1;
unsigned short syncTransfer:1;
unsigned short restartDMA:1;
unsigned short reserved:5;
}bmTranFlags;
unsigned short errorCount;
unsigned short waitSOFCount;
unsigned char usedDMACh;
}URB_INFO;
/*****************************************
*Function prototype declaration
*****************************************/
Inline void CheckCHxIntStat( unsigned char chNum );
Inline unsigned char DMATransactionEnd( unsigned char dmaCHNum );
Inline void TransactionEnd( unsigned char chNum );
Inline long CheckCHNumber( unsigned char chNum );
Inline unsigned short GetURBCmpStatus( URB_INFO *psURBInfo );
Inline unsigned short GetURBErrStatus( unsigned char conditionCode );
Inline void UpdateURBInfo( URB_INFO *psURBInfo, unsigned long copyCount );
Inline void UpdateURB( URB_INFO *psURBInfo, unsigned short status );
Inline unsigned long ReadFIFOData( unsigned char chNum, unsigned char *pBufAdrs, unsigned long dataSize );
Inline unsigned long WriteFIFOData( unsigned char chNum, unsigned char *pBufAdrs, unsigned long dataSize );
Inline void ReadRAMData( unsigned long ramAdrs, unsigned char *pBufAdrs, unsigned long dataSize );
Inline void WriteRAMData( unsigned long ramAdrs, unsigned char *pBufAdrs, unsigned long dataSize );
/*****************************************
*Macros declaration
*****************************************/
/*****************************************
*Variables declaration
*****************************************/
#ifdef DEBUG_C
HC_MANAGER HCStatus;
URB_INFO URBInfo[NUM_USB_CH];
#else /* #ifdef DEBUG_C */
static HC_MANAGER HCStatus;
static URB_INFO URBInfo[NUM_USB_CH];
#endif /* #ifdef DEBUG_C */
static const unsigned char TestPacket[]= {
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,
0xAA,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,
0xEE,0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
0xFF,0xFF,0xFF,0xFF,0xFF,0x7F,0xBF,0xDF,
0xEF,0xF7,0xFB,0xFD,0xFC,0x7E,0xBF,0xDF,
0xEF,0xF7,0xFB,0xFD,0x7E};
static unsigned char SavePortSpeed;
/*=============================================================================================
// Function_Name: USBH_HCDS_HCDetect
//
// description : Host Contoller existence detection
//
// Detected if Host Contoller existed
//
// argument : None
//
// return : STATUS_SUCCESS Processing is completed successfully
// STATUS_NO_DEVICE Device doesn't exist
===============================================================================================*/
long USBH_HCDS_HCDetect( void )
{
/*=================================/
Confirm the existence by whether revision can be read /
/=================================*/
if( RegRead(REG08_RevisionNum) != REVISION_NUMBER ){
return STATUS_NO_DEVICE;
}
return STATUS_SUCCESS;
}
/*=============================================================================================
// Function_Name: USBH_HCDS_HCReset
//
// description : Host Controller reset process
//
// Reset Host Contorller and do initialization
//
// argument : None
//
// return : None
===============================================================================================*/
void USBH_HCDS_HCReset( void )
{
unsigned char creClkSelect;
unsigned char creChipConfig;
volatile unsigned char temp;
/*=======================/
Initialize variables for management/
/=======================*/
memset(&HCStatus, 0, sizeof(HCStatus));
memset(URBInfo, 0, sizeof(URBInfo));
if( USBH_HCD_USED_DMA_FOR_IDE == 1 ){
HCStatus.bmFlags.usedDMAforIDE = 1;
}
if( HCStatus.bmFlags.usedDMAforIDE == 1 ){
/* DMA of CPU I/F is used with IDE */
/* The DMA channel number of CPU I/F used with IDE is saved */
HCStatus.usedDMAChforIDE = (USBH_HCD_USED_DMACH_FOR_IDE & MASK_CPU_DMACH);
}
if( USBH_HCD_DIS_CHIRP_FINISH == 1 ){
/* Make the detecting function effective even NG in chirp detecting */
HCStatus.bmFlags.disChirpOff = 1;
}
/*=======================================/
Initialize the register for the host function/
/=======================================*/
if( RegRead(REG16_ModeProtect) == MODE_PROTECT_OFF ){
/* When the operation setting of this LSI is not done */
/*=================/
Set Chip configuration/
/=================*/
creChipConfig = ((USBH_HCD_CHIP_INT_LEVEL & MASK_1BIT) << 7);
creChipConfig |= ((USBH_HCD_CHIP_INT_MODE & MASK_1BIT) << 6 );
creChipConfig |= ((USBH_HCD_CHIP_DREQ_LEVEL & MASK_1BIT) << 5 );
creChipConfig |= ((USBH_HCD_CHIP_DACK_LEVEL & MASK_1BIT) << 4 );
creChipConfig |= ((USBH_HCD_CHIP_CS_MODE & MASK_1BIT) << 3 );
creChipConfig |= ((USBH_HCD_CHIP_CPU_ENDIAN & MASK_1BIT) << 2 );
creChipConfig |= (USBH_HCD_CHIP_BUS_MODE & MASK_2BIT);
creClkSelect = ((USBH_HCD_CHIP_ACT_IDE_TERM & MASK_1BIT) << 7);
creClkSelect = ((USBH_HCD_CHIP_ACT_DD_TERM & MASK_1BIT) << 6);
creClkSelect = ((USBH_HCD_CHIP_PORT1_X_2 & MASK_1BIT) << 1);
creClkSelect = (USBH_HCD_CHIP_CLK_SELECT & MASK_1BIT);
RegWrite(REG08_ChipConfig, creChipConfig); // Chip config set
temp = *(volatile unsigned char *)0xCC0000B9; // Reading and do nothing
RegWrite(REG08_ClkSelect, creClkSelect);
RegWrite(REG08_ModeProtect, 0x00);
/*======================/
Set OSC return waiting time/
/======================*/
RegWrite(REG16_WakeupTim, USBH_HCD_OSC_WAKEUP_TIME);
}
// ResetDTM is cleared when it is 1 port operation
if( ( RegRead(REG08_ClkSelect) & 0x02 ) == 0x02 ) {
RegModify( REG08_HostDeviceSel, MASK_HOSTxDEVICE, BIT_HOSTxDEVICE_DEVICE );
RegClear( REG08_D_Reset, BIT_ResetDTM );
}
/*===================/
Host register selection/
/===================*/
RegModify(REG08_HostDeviceSel, MASK_HOSTxDEVICE, BIT_HOSTxDEVICE_HOST );
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