usbh_hcds_user_config.c

epson usb2.0 控制芯片 S1R72V05 固件程序。

/*
 *	description	: USBH HCD User Configuration(static)
 *	Maker		: Hiromichi Kondo
 *	Copyright	: (C)2005,SEIKO EPSON Corp. All Rights Reserved.
 */


#include <reg_mx21.h>			/* Please change it by the used environment */
#include <toya2_pdic_timer.h>	/* Please change it by the used environment */
#include <OSCall.h>				/* Please change it by the used environment */
#include <usbh_hcd.h>
#include <usbh_hcds_common.h>
#include <SPRDEF.h>
#include <SPRSTS.h>
#include <usbh_hcds_user_config.h>



/*****************************************
 * Define definition
 *****************************************/
#define CPUDMACH				(0)				/* DMA channel number 0 of CPU */
#define CPUDMA_IRQ				(32)			/* IRQ 32 */
#define CPUTIMERCH				(2)				/* Timer channel number 2  of CPU */
#define CPUTIMER_IRQ			(27-CPUTIMERCH)	/* IRQ 24 - 26 */
#define TIMER_1MS_COUNT			(16*1024)		/* 1ms in 16MHz */

/*****************************************
 * Structure definition
 *****************************************/

/*****************************************
 * Function prototype declaration
 *****************************************/
void CPUDMACmpHandler( void );
void CPUTimerCmpHandler( void );
extern void flush_Dcache(unsigned long, unsigned long); 	  /* D-Cache Invalidate for MVA entry */
extern void clean_Dcache(unsigned long, unsigned long); 	  /* D-Cache clean for MVA entry */

/*****************************************
 * Macro declaration
 *****************************************/

/*****************************************
 * Variable  declaration
 *****************************************/
static CALLBACK_PROC pfnCPUDMACmp;
static CALLBACK_PROC pfnCPUTimerCmp;

/*=============================================================================================
// Function_Name: USBH_HCDS_CPUDMAStart
//
// description	: Start transfer with DMA implemented on CPU.
//
//				  Set the parameter to DMA implemented on CPU, and start to transfer
//
// argument 	: dir						(in)Direction of transfer
//												0:Receive(this IC ->CPU)
//												1:Send(CPU ->this IC)
//				  *pSrcAdrs					(in)Source address
//				  *pDesAdrs					(in)Destination address
//				  size						(in)Number of transfer Bytes
//				  pfnCallback				(in)Pointer of callback function
//
// return		: None
===============================================================================================*/
void USBH_HCDS_CPUDMAStart( unsigned char dir, void *pSrcAdrs, void *pDesAdrs,
								unsigned long size, CALLBACK_PROC pfnCallback )
{
	/*
		Call this API before starting DMA of this IC.
		Please do the setting and the transfer execution concerning DMA implemented on CPU in this API.

		If the pointer of the callback function passed by the argument is out of NULL,
		please call it when the DMA transfer implemented on CPU completed.

		The source address and the destination address are set as follows, according to the direction of transfer.
		Please set DMA implemented on CPU properly.
		<Transfer direction: reveive>
			  Source address = fixed(address of DMA0/1_RdData_H of this IC)
			  Destination address = increment
		<Transfer direction: send>
			  Source address = increment
			  Destination address = fixed(address of DMA0/1_RdData_H of this IC)
		As for the number of transfer bytes passed by the argument, it is set as the transfer buffer length specified with URB.
		Pay attention that the data length will not be confirmed
	*/


//	const T_DINH dinh_CPUDMA_handler = { TA_HLNG, CPUDMACmpHandler ,1 };
		/* Variable for NORTi interrupt handler registration(priority 1) */
	unsigned char fraction;
	unsigned long count;
	OS_BOOL	bCpuState;


	pfnCPUDMACmp = pfnCallback;


	bCpuState = OS_SnsLoc();
	if (bCpuState != OS_TRUE ){
		/* If CPU is not locked, lock it. */
		if( OS_SnsCtx() == TRUE ){
	 		OS_ILocCpu();
		} else {
		 	OS_LocCpu();
		}
	}

//	OS_DefInh( CPUDMA_IRQ, (T_DINH *)&dinh_CPUDMA_handler );
	OS_EnaInt( CPUDMA_IRQ );

	if (bCpuState != OS_TRUE ){
		if( OS_SnsCtx() == TRUE ){
	 		OS_IUnlCpu();
		} else {
		 	OS_UnlCpu();
		}
	}

	/* Enable interrupt of DMA Ch0 */
	rlMX21_DIMR &= ~1;

	/* DMA Ch0 source address register setting */
	rlMX21_SAR0 = (unsigned long)pSrcAdrs;

	/* DMA Ch0 destination address register setting */
	rlMX21_DAR0 = (unsigned long)pDesAdrs;


	count = size;

	fraction = (unsigned char)size & 0x01;
	if( fraction == 1 ){
		count++;
	}

	/* DMA Ch0 transfer count register setting */
	rlMX21_CNTR0 = count;

	/* DMA Ch0 transfer burst length register setting */
	rlMX21_BLR0 = 16;

	if( dir == 0 ){
		/* Reveive(this IC -> CPU) */

		/* Data cache flash & clear */
		flush_Dcache((unsigned long)pDesAdrs, size);
		clean_Dcache((unsigned long)pDesAdrs, size);

		// DMA Ch0 control register setting
		rlMX21_CCR0 =
						(0<<14) |	/* ACRPT : 0 or 1  :Auto Clear Off */
						(0<<12) |	/* DMOD  : 0 - 3   :Dst Linear Mem */
						(2<<10) |	/* SMOD  : 0 - 3   :Src FIFO	   */
						(0<< 9) |	/* MDIR  : 0 or 1  :Direction: Inc */
						(0<< 8) |	/* MSEL  : 0 or 1  :N/A 		   */
						(0<< 6) |	/* DSIZ  : 0 - 3   :dst 32bit Port */
						(2<< 4) |	/* SSIZ  : 0 - 3   :src 16bit Port */
						(1<< 3) |	/* REN	 : 0 or 1  :Request Enable */
						(0<< 2) |	/* RPT	 : 0 or 1  :Repeat Disable */
						(0<< 1) |	/* FRC	 : 0 or 1  :Force DMA Non  */
						(0<< 0) ;	/* CEN	 : 0 or 1  :Enable DMA Ch  */
	} else {
		/* Send(CPU -> this IC)  */

		/* Data cache flash & clear */
		flush_Dcache((unsigned long)pSrcAdrs, size);
		clean_Dcache((unsigned long)pSrcAdrs, size);

		// DMA Ch0 control register setting
		rlMX21_CCR0 =
						(0<<14) |	/* ACRPT : 0 or 1  :Auto Clear Off */
						(2<<12) |	/* DMOD  : 0 - 3   :Dst FIFO	   */
						(0<<10) |	/* SMOD  : 0 - 3   :Src Linear Mem */
						(0<< 9) |	/* MDIR  : 0 or 1  :Direction: Inc */
						(0<< 8) |	/* MSEL  : 0 or 1  :N/A 		   */
						(2<< 6) |	/* DSIZ  : 0 - 3   :dst 16bit Port */
						(0<< 4) |	/* SSIZ  : 0 - 3   :src 32bit Port */
						(1<< 3) |	/* REN	 : 0 or 1  :Request Enable */
						(0<< 2) |	/* RPT	 : 0 or 1  :Repeat Disable */
						(0<< 1) |	/* FRC	 : 0 or 1  :Force DMA Non  */
						(0<< 0) ;	/* CEN	 : 0 or 1  :Enable DMA Ch  */
	}

	// DMA Ch0 control register setting
	rlMX21_CCR0 |=
					(0<<14) |	/* ACRPT : 0 or 1  :Auto Clear Off */
					(0<<12) |	/* DMOD  : 0 - 3   :Dst FIFO	   */
					(0<<10) |	/* SMOD  : 0 - 3   :Src Linear Mem */
					(0<< 9) |	/* MDIR  : 0 or 1  :Direction: Inc */
					(0<< 8) |	/* MSEL  : 0 or 1  :N/A 		   */
					(0<< 6) |	/* DSIZ  : 0 - 3   :dst 16bit Port */
					(0<< 4) |	/* SSIZ  : 0 - 3   :src 32bit Port */
					(0<< 3) |	/* REN	 : 0 or 1  :Request Enable */
					(0<< 2) |	/* RPT	 : 0 or 1  :Repeat Disable */
					(0<< 1) |	/* FRC	 : 0 or 1  :Force DMA Non  */
					(1<< 0) ;	/* CEN	 : 0 or 1  :Enable DMA Ch  */

}

/*=============================================================================================
// Function_Name: USBH_HCDS_CPUDMAStop
//
// description	: Stop the transfer of DMA implemented on CPU
//
//				  DMA implemented on CPU is stopped
//
// argument 	: None
//
// return		: None
===============================================================================================*/
void USBH_HCDS_CPUDMAStop( void )
{
	rlMX21_CCR0 = 0;
	rlMX21_DISR |= 1;	/* Clear the interrupt status */
}

/*=============================================================================================
// Function_Name: CPUDMACmpHandler
//
// description	: Interrupt process of DMA implemented on CPU
//
//				  Process the transfer end interrupt of DMA implemented on CPU
//
// argument 	: None
//
// return		: None
===============================================================================================*/
void CPUDMACmpHandler( void )
{
	rlMX21_CCR0 = 0;
	rlMX21_DISR |= 1;	/* Interrupt status clear */

	USBH_HCDS_ExecCallback(pfnCPUDMACmp, CPUDMACH, 0, NULL);
}

/*=============================================================================================
// Function_Name: USBH_HCDS_CPUTimerStart
//
// description	: Start the timer implemented on CPU
//
//				  Start the timer implemented on CPU. This timer is used to wait for the waiting
				  time of recovering from VBUS overcurrent
//
// argument 	: pfnCallback				(in)Pointer of callback function
//
// return		: None
===============================================================================================*/
void USBH_HCDS_CPUTimerStart( CALLBACK_PROC pfnCallback )
{
	/*
	   After the overcurrent of VBUS is detected with this IC and VBUS is turned Off, call this API.
	   Please do the setting and the transfer execution concerning the timer implemented on CPU in this API.

	   If the pointer of the callback function passed by the argument is out of NULL,
	   please call it when the DMA transfer implemented on CPU completed
	*/
	OS_BOOL	bCpuState;

//	const T_DINH dinh_CPUTimer_handler = { TA_HLNG, CPUTimerCmpHandler ,1 };
		/* Variable for NORTi interrupt handler registration(priority 1)*/


	pfnCPUTimerCmp = pfnCallback;

	/* Set Timer2 */
	*((unsigned long *)0x10004008) = TIMER_1MS_COUNT;
	TOYA2_GPTimerSetting(CPUTIMERCH, 0x00000212);	/* Set the timer(GPT Control Register 2) */
	TOYA2_GPTimerStart(CPUTIMERCH);		/* Start the timer */

	bCpuState = OS_SnsLoc();
	if (bCpuState != OS_TRUE ){
		/* If CPU is not locked, lock it. */
		if( OS_SnsCtx() == TRUE ){
	 		OS_ILocCpu();
		} else {
		 	OS_LocCpu();
		}
	}

//	OS_DefInh( CPUTIMER_IRQ, (T_DINH *)&dinh_CPUTimer_handler );
	OS_EnaInt( CPUTIMER_IRQ );

	if (bCpuState != OS_TRUE ){
		if( OS_SnsCtx() == TRUE ){
	 		OS_IUnlCpu();
		} else {
		 	OS_UnlCpu();
		}
	}


}

/*=============================================================================================
// Function_Name: USBH_HCDS_CPUTimerStop
//
// description	: Stop the timer implemented on CPU
//
//				  The timer implemented on CPU is stopped
//
// argument 	: None
//
// return		: None
===============================================================================================*/
void USBH_HCDS_CPUTimerStop( void )
{
	/* Because it doesn't act in Toppers version, so changed the disable timing of Timer interrupt */
	OS_DisInt( CPUTIMER_IRQ );
	TOYA2_GPTimerStop(CPUTIMERCH);			/* Stop the timer */
}

/*=============================================================================================
// Function_Name: CPUTimerCmpHandler
//
// description	: Interrupt process for timer implemented on CPU
//
//				  Process for the transfer end interrupt of the timer implemented on CPU
//
// argument 	: None
//
// return		: None
===============================================================================================*/
void CPUTimerCmpHandler( void )
{
	TOYA2_GPTimerStop(CPUTIMERCH);			/* Stop the timer */
	OS_DisInt( CPUTIMER_IRQ );
	USBH_HCDS_ExecCallback(pfnCPUTimerCmp, 0, 0, NULL);
}