📄 drvacs.h
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#ifndef DRIVE_ACCESS_H
#define DRIVE_ACCESS_H
/* 2006.04.25 S.Niiyama Modify */
/* #include "sprdef.h" */
#include "SPRDEF.h"
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////// [ User definition ] ////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#define FOR_NOT_USE_VARIABLE 1 // Remove un-used or un-referenced variable(warning subject of ARM compiler).
#define FOR_HARD_DIRECTCOPY 2 // Implement direct file copy according to hardware ( Sapporo S1R72V05 board specification) and device driver special function
#ifdef TOYA2_C
#define LDRV_SECTOR_BUF_ADDRESS 0xC3000000
#else
#define LDRV_SECTOR_BUF_ADDRESS 0x10010000
#endif
#define MAX_DEVICE 3 /* will be changed according to the number of device connected in lower part */
#define MAX_DEVICE_NUM MAX_DEVICE
#define MAX_DRIVE_NUM_FOR_DEVICE 0x01
#define MAX_DRIVE_NUM MAX_DEVICE * MAX_DRIVE_NUM_FOR_DEVICE
#define MAX_DRIVER MAX_GDIC /* Number of lower driver */
#define MAX_ID 0x05 /* Max ID number can be assigned */
// Hierarchy implemented
#define DEF_SDRV_HIERARCHY // Sync. layer
#define DEF_LDRV_HIERARCHY // Logical layer
#define DEF_PDRV_HIERARCHY // Physical layer
// GDIC implemented
#define DEF_IDE_GDIC /* 2005.04.08 Yanagihara */
#define DEF_CF_GDIC
//#define DEF_SD_GDIC
//#define DEF_MMC_GDIC
//#define DEF_SM_GDIC
//#define DEF_NAND_GDIC
//#define DEF_RAM_GDIC
#define DEF_MS_GDIC /* 2005.04.04 H.Kondo */
#ifdef DEF_PDRV_HIERARCHY /* Physical layer is implemented */
#define DEVCALL(x) 0 /* Call routines of physical layer since physical layer is implemented */
#else // DEF_PDRV_HIERARCHY
#define DEVCALL(x) x /* Call routines of GDIC layer since physical layer is not implemented */
#endif // DEF_PDRV_HIERARCHY
// Declaration of number of hierarchy
#define LOWERLAYER_Hierarchy 0x00 /* Lower layer ( fixed ) under the file system layer */
enum {
#ifdef DEF_SDRV_HIERARCHY /* Sync. layer is implemented */
SDRV_Hierarchy,
#endif
#ifdef DEF_LDRV_HIERARCHY /* Logical layer is implemented */
LDRV_Hierarchy,
#endif
#ifdef DEF_PDRV_HIERARCHY /* Physical layer is implemented */
PDRV_Hierarchy,
#endif
GDIC_Hierarchy,
MAX_Hierarchy
};
// Declaration of number of GDIC drive
enum {
#ifdef DEF_MS_GDIC /* MS-Device layer is implemented */
MS_GDIC,
#endif
#ifdef DEF_IDE_GDIC /* IDE-Device layer is implemented */
IDE_GDIC,
#endif
#ifdef DEF_CF_GDIC /* CF-Device layer is implemented */
CF_GDIC,
#endif
#ifdef DEF_SD_GDIC /* SD-Device layer is implemented */
SD_GDIC,
#endif
#ifdef DEF_MMC_GDIC /* MMC-Device layer is implemented */
MMC_GDIC,
#endif
#ifdef DEF_SM_GDIC /* SM-Device layer is implemented */
SM_GDIC,
#endif
#ifdef DEF_NAND_GDIC /* NAND-Device layer is implemented */
NAND_GDIC,
#endif
#ifdef DEF_RAM_GDIC /* RAM-Device layer is implemented */
RAM_GDIC,
#endif
#if 0 // 2004.4.21 Yanagihara
#ifdef DEF_MS_GDIC /* MS-Device layer is implemented */
MS_GDIC,
#endif
#endif
MAX_GDIC
};
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////[Variable definition]Do not change following items ////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#define READ6 0x08 /* ATAPI Read6 Command */
#define WRITE6 0x0A /* ATAPI Write6 Command */
#define READ10 0x28 /* ATAPI Read10 Command */
#define WRITE10 0x2A /* ATAPI Write10 Command */
#define READ12 0xA8 /* ATAPI Read12 Command */
#define WRITE12 0xAA /* ATAPI Write12 Command */
#define SYNC_CACHE 0x35 /* ATAPI SynchronizeCache Command */
#define TEST_UNIT_READY 0x00 /* ATAPI TestUnitReady Command */
#define FORMAT_UNIT 0x04 /* ATAPI FormatUnit Command */
#define WRITE_BUFFER 0x3B /* ATAPI WriteBuffer Command */
#define READ_BUFFER 0x3C /* ATAPI ReadBuffer Command */
/* Device Type */
#define DRV_FUNC_HDD 0x00 /* Hard disk */
#define DRV_FUNC_CD 0x05 /* CD/CD-RW/DVD drive */
#define DRV_FUNC_MO 0x07 /* MO drive */
#define DRV_FUNC_SD 0x12 /* SD drive */
#define DRV_FUNC_NAND 0x13 /* NAND drive (SMT) */
#define DRV_FUNC_CF 0x14 /* CF drive */
#define DRV_FUNC_UNKNOWN 0xFF /* unknown */
/* Data Transfer Mode */
#define DRV_FUNC_PIO_MODE 0x00 /* PIO Transmission mode */
#define DRV_FUNC_DMA_MODE 0x01 /* DMA Transmission mode */
#define DRV_FUNC_DIRECTCOPY_MODE 0x02 /* DIRECT COPY Transmission mode (according hard function) */
/* Data Transfer Direction */
#define DRV_FUNC_IN 0x00 /* Receiving data from device */
#define DRV_FUNC_OUT 0x01 /* Sending data to device */
/* Command Type */
#define DRV_FUNC_ATA 0x00 /* ATA command */
#define DRV_FUNC_ATAPI 0x01 /* ATAPI command */
/* Device Status */
#define DRV_FUNC_CMD_STOP 0x00 /* Command under suspension */
#define DRV_FUNC_CMD_EXEC 0x01 /* Command on executing */
#define DRV_FUNC_CMD_COMP 0x02 /* Command finished */
#define DRV_FUNC_ID_ERR 0x03 /* Specified ID error */
#define DRV_FUNC_ID_EXEC 0x04 /* Specified device is executing in other ID */
#define DRV_FUNC_BSY 0x05 /* Specified device is in BSY state */
#define DRV_FUNC_TRAN_READY 0x06 /* Transmitting ready */
#define DRV_FUNC_DEVICE_ERR 0x07 /* Error occurrence in device */
#define DRV_FUNC_CRC_ERR 0x08 /* CRC error */
#define DRV_FUNC_WP_ERR 0x09 /* Write-protect error */
#define DRV_FUNC_MC_ERR 0x0A /* Error of media exchanged */
#define DRV_FUNC_IDNF_ERR 0x0B /* Address error */
#define DRV_FUNC_MCR_ERR 0x0C /* Detecting media */
#define DRV_FUNC_ABORT_ERR 0x0D /* Command is suspended */
#define DRV_FUNC_NM_ERR 0x0E /* Media is not exist */
#define DRV_FUNC_PIOIN_READY 0x10 /* PIO DATA IN READY */
#define DRV_FUNC_PIOOUT_READY 0x11 /* PIO DATA OUT READY */
/* Device DMA Status */
#define DRV_DMA_FUNC_STOP 0x00 /* DMA Command under suspension */
#define DRV_DMA_FUNC_EXEC 0x01 /* DMA Command on executing */
#define DRV_DMA_FUNC_COMP 0x02 /* DMA Command finished */
/* Data Transfer Mode */
#define DRV_FUNC_PIO 0x00 /* IDE PIO Data Transfer */
#define DRV_FUNC_MULTI 0x01 /* IDE MutiWord DMA Data Transfer */
#define DRV_FUNC_ULTRA 0x02 /* IDE ULTRA DMA Data Transfer */
/* Funcution Module Open Status */
#define DRV_FUNC_MODULE_CLOSE 0x00 /* CLOSE: not available */
#define DRV_FUNC_MODULE_OPEN 0x01 /* OPEN: available */
/* Command Execute Retry Count */
#define DRV_COMMANDEXEC_RETRY_CNT 0x03 // Set the number of times of retry after error occuring in command execution
#define FREE_ID 0x00 /* Free ID */
#define ALLOC_ID 0x01 /* Assign ID */
#define FIRST_OPEN 0x01 /* IDE Function Module Firat Open Check */
#define NO_DEVICE 0xFF /* DEVICE Type Initialize */
#define ENABLE 0x00 /* Permission */
#define DISABLE 0x01 /* Prohibition */
#define BIT_OFF 0x00 /* flag for CBR */
#define BIT_ON 0x01 /* flag for CBR */
/* Type of partition */
#define FAT_PAR_UNKNOWN 0xFF // NULL or Unnown (Unknown or deleted if iNumSec is zero)
#define FAT_PAR_FAT12 0x01 //FAT12(MS-DOS 12-bit BPB/FAT < 16MB)
#define FAT_PAR_FAT16_1 0x04 //FAT16<32MB(MS-DOS 16-bit BPB/FAT < 32MB)
#define FAT_PAR_EXT 0x05 // Extented partition(Extended MS-DOS partition)
#define FAT_PAR_FAT16_2 0x06 //FAT16(big)>=32MB(MS-DOS 16-bit BPB/FAT >= 32MB)
#define FAT_PAR_FAT32_1 0x0B //FAT32
#define FAT_PAR_FAT32_2 0x0C //FAT32X(LBA)
#define FAT_PAR_FAT16_3 0x0E //FAT16X(LBA)
#define FAT_WORD_PEEK(p) ((((unsigned short)*((unsigned char *)(p) + 1)) << 8) | (unsigned short)*((unsigned char *)(p)))
#define FAT_DWORD_PEEK(p) ((((unsigned long)*((unsigned char *)(p) + 3)) << 24) | (((unsigned long)*((unsigned char *)(p) + 2)) << 16) | \
(((unsigned long)*((unsigned char *)(p) + 1)) << 8) | (unsigned long)*((unsigned char *)(p)))
#define FAT_WORD_POKE(p, wData) { \
*(unsigned char *)(p) = (unsigned char)(wData & 0xff); \
*((unsigned char *)(p) + 1) = (unsigned char)((wData >> 8) & 0xff); \
}
#define FAT_DWORD_POKE(p, ulData) { \
*(unsigned char *)(p) = (unsigned char)(ulData & 0xff); \
*((unsigned char *)(p) + 1) = (unsigned char)((ulData >> 8) & 0xff); \
*((unsigned char *)(p) + 2) = (unsigned char)((ulData >> 16) & 0xff); \
*((unsigned char *)(p) + 3) = (unsigned char)((ulData >> 24) & 0xff); \
}
/* Device List Parameter */
typedef struct driveaccessdevicelist{
UCHAR deviceCount; /* Number of connected devices */
UCHAR deviceType[MAX_DEVICE]; /* Device type */
}DRIVEACCESS_FUNCDEVICELIST;
/* Device Command Parameter */
typedef struct driveaccesscmdpara{
UCHAR commandMode; /* ATA/ATAPI command type */
UCHAR commandBlock[12]; /* Command block */
}DRIVEACCESS_FUNCCMDPARA;
/* Transfer Parameter */
typedef struct driveaccesstranpara{
UCHAR direction; /* Transfer direction */
ULONG dataSize; /* Number of bytes of transfer data */
ULONG dataPointer; /* Buffer pointer of transfer data */
ULONG transferSize; /* Un-used */
}DRIVEACCESS_FUNCTRANPARA;
typedef struct cbrid{
USHORT cbrID;
USHORT allocID;
}DRIVEACCESS_CBR_ID;
typedef struct driveaccessfunctiontable{
LONG ( *Reset )( void );
LONG ( *Open )( void );
LONG ( *Close )( void );
LONG ( *AllocID )( USHORT *pAllocId );
LONG ( *FreeID )( USHORT id );
LONG ( *DeviceReset )( USHORT id, USHORT deviceNo );
LONG ( *GetDeviceList )( USHORT id, UCHAR *pList );
LONG ( *GetDeviceParameter )( USHORT id, USHORT deviceNo, UCHAR *pDataptr );
LONG ( *CommandOut )( USHORT id, USHORT deviceNo, UCHAR transferMode, DRIVEACCESS_FUNCCMDPARA *pCmdBlock, DRIVEACCESS_FUNCTRANPARA *pTranPara );
LONG ( *CommandStop )( USHORT id, USHORT deviceNo );
LONG ( *DMAStart )( USHORT id, USHORT deviceNo, UCHAR transferMode, DRIVEACCESS_FUNCTRANPARA *pTranPara );
LONG ( *DMAStop )( USHORT id, USHORT deviceNo );
LONG ( *GetDMAStatus )( USHORT id, USHORT deviceNo, ULONG *pStatus );
LONG ( *SoftDataTransfer )( USHORT id, USHORT deviceNo, UCHAR transferMode, DRIVEACCESS_FUNCTRANPARA *pTranPara );
LONG ( *GetStatus )( USHORT id, USHORT deviceNo, ULONG *pStatus, ULONG *pTransferSize, UCHAR *pSenseData );
LONG ( *SyncCommand )( USHORT id, USHORT deviceNo, UCHAR transferMode, DRIVEACCESS_FUNCCMDPARA *pCmdBlock, DRIVEACCESS_FUNCTRANPARA *pTranPara, ULONG *pStatus, UCHAR *pSenseData );
LONG ( *RegisterCBRDMAComp )( USHORT id, USHORT cbrID, USHORT deviceNo, CALLBACK_PROC pfNotifyDmaComp );
LONG ( *UnregisterCBRDMAComp )( USHORT id, USHORT cbrID, USHORT deviceNo, CALLBACK_PROC pfNotifyDmaComp );
LONG ( *RegisterCBRIntrq )( USHORT id, USHORT cbrID, USHORT deviceNo, CALLBACK_PROC pfNotifyIntrq );
LONG ( *UnregisterCBRIntrq )( USHORT id, USHORT cbrID, USHORT deviceNo, CALLBACK_PROC pfNotifyIntrq );
}DRIVEACCESS_FUNCTIONTABLE;
#ifdef DEF_SDRV_HIERARCHY /* Sync. layer is implemented */
extern DRIVEACCESS_FUNCTIONTABLE SDRVFuncAccessTable;
#endif
#ifdef DEF_LDRV_HIERARCHY /* Logical layer is implemented */
extern DRIVEACCESS_FUNCTIONTABLE LDRVFuncAccessTable;
#endif
#ifdef DEF_PDRV_HIERARCHY /* Physical layer is implemented */
extern DRIVEACCESS_FUNCTIONTABLE PDRVFuncAccessTable;
#endif
#ifdef DEF_IDE_GDIC /* IDE-Device layer is implemented */
extern DRIVEACCESS_FUNCTIONTABLE IDEFuncAccessTable;
#endif
#ifdef DEF_CF_GDIC /* CF-Device layer is implemented */
extern DRIVEACCESS_FUNCTIONTABLE CFFuncAccessTable;
#endif
#ifdef DEF_SD_GDIC /* SD-Device layer is implemented */
extern DRIVEACCESS_FUNCTIONTABLE SDFuncAccessTable;
#endif
#ifdef DEF_MMC_GDIC /* MMC-Device layer is implemented */
extern DRIVEACCESS_FUNCTIONTABLE MMCFuncAccessTable;
#endif
#ifdef DEF_SM_GDIC /* SM-Device layer is implemented */
extern DRIVEACCESS_FUNCTIONTABLE SMFuncAccessTable;
#endif
#ifdef DEF_NAND_GDIC /* NAND-Device layer is implemented */
extern DRIVEACCESS_FUNCTIONTABLE NANDFuncAccessTable;
#endif
#ifdef DEF_RAM_GDIC /* RAM-Device layer is implemented */
extern DRIVEACCESS_FUNCTIONTABLE RAMFuncAccessTable;
#endif
#ifdef DEF_MS_GDIC /* MS-Device layer is implemented */
extern DRIVEACCESS_FUNCTIONTABLE MSFuncAccessTable;
#endif
extern DRIVEACCESS_FUNCTIONTABLE *pDriverAccess[];
extern DRIVEACCESS_FUNCTIONTABLE *pDeviceAccess[];
extern void Hierarchy_Func_Init( void );
#endif //#ifndef DRIVE_ACCESS_H
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