reg_mx21.h

epson usb2.0 控制芯片 S1R72V05 固件程序。

/*
 * @file   reg_mx21.h
 * @brief  Dragonball i.MX21 Register Definition
 * @author 2005/06/03 Masatoshi Kawashima
 * Copyright (C)SEIKO EPSON Corp. All Rights Reserved.
 */

#ifndef _REG_MX21_H_
#define _REG_MX21_H_

/*
 * SYSCTRL
 */
#define DMX21_REG_SYSCTRL_BASE		0x10027804
#define rlMX21_SIDR1		*(volatile unsigned long*)(DMX21_REG_SYSCTRL_BASE+0x00)
#define rlMX21_SIDR2		*(volatile unsigned long*)(DMX21_REG_SYSCTRL_BASE+0x04)
#define rlMX21_SIDR3		*(volatile unsigned long*)(DMX21_REG_SYSCTRL_BASE+0x08)
#define rlMX21_SIDR4		*(volatile unsigned long*)(DMX21_REG_SYSCTRL_BASE+0x0C)
#define rlMX21_FMCR			*(volatile unsigned long*)(DMX21_REG_SYSCTRL_BASE+0x10)
#define rlMX21_GPCR			*(volatile unsigned long*)(DMX21_REG_SYSCTRL_BASE+0x14)
#define rlMX21_WBCR			*(volatile unsigned long*)(DMX21_REG_SYSCTRL_BASE+0x18)
#define rlMX21_DSCR1		*(volatile unsigned long*)(DMX21_REG_SYSCTRL_BASE+0x1C)
#define rlMX21_DSCR2		*(volatile unsigned long*)(DMX21_REG_SYSCTRL_BASE+0x20)
#define rlMX21_DSCR3		*(volatile unsigned long*)(DMX21_REG_SYSCTRL_BASE+0x24)
#define rlMX21_DSCR4		*(volatile unsigned long*)(DMX21_REG_SYSCTRL_BASE+0x28)
#define rlMX21_DSCR5		*(volatile unsigned long*)(DMX21_REG_SYSCTRL_BASE+0x2C)
#define rlMX21_DSCR6		*(volatile unsigned long*)(DMX21_REG_SYSCTRL_BASE+0x30)
#define rlMX21_DSCR7		*(volatile unsigned long*)(DMX21_REG_SYSCTRL_BASE+0x34)
#define rlMX21_DSCR8		*(volatile unsigned long*)(DMX21_REG_SYSCTRL_BASE+0x38)
#define rlMX21_DSCR9		*(volatile unsigned long*)(DMX21_REG_SYSCTRL_BASE+0x3C)
#define rlMX21_DSCR10		*(volatile unsigned long*)(DMX21_REG_SYSCTRL_BASE+0x40)
#define rlMX21_DSCR11		*(volatile unsigned long*)(DMX21_REG_SYSCTRL_BASE+0x44)
#define rlMX21_DSCR12		*(volatile unsigned long*)(DMX21_REG_SYSCTRL_BASE+0x48)
#define rlMX21_PCSR			*(volatile unsigned long*)(DMX21_REG_SYSCTRL_BASE+0x4C)


/*
 * ARM Interrupt Controller
 */
#define DMX21_REG_AITC_BASE			0x10040000
#define rlMX21_INTCNTL		*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x00)
#define rlMX21_NIMASK		*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x04)
#define rlMX21_INTENNUM		*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x08)
#define rlMX21_INTDISNUM	*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x0C)
#define rlMX21_INTENABLEH	*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x10)
#define rlMX21_INTENABLEL	*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x14)
#define rlMX21_INTTYPEH		*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x18)
#define rlMX21_INTTYPEL		*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x1C)
#define rlMX21_NIPRIORITY7	*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x20)
#define rlMX21_NIPRIORITY6	*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x24)
#define rlMX21_NIPRIORITY5	*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x28)
#define rlMX21_NIPRIORITY4	*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x2C)
#define rlMX21_NIPRIORITY3	*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x30)
#define rlMX21_NIPRIORITY2	*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x34)
#define rlMX21_NIPRIORITY1	*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x38)
#define rlMX21_NIPRIORITY0	*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x3C)
#define rlMX21_NIVECSR		*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x40)
#define rlMX21_FIVECSR		*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x44)
#define rlMX21_INTSRCH		*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x48)
#define rlMX21_INTSRCL		*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x4C)
#define rlMX21_INTFRCH		*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x50)
#define rlMX21_INTFRCL		*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x54)
#define rlMX21_NIPNDH		*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x58)
#define rlMX21_NIPNDL		*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x5C)
#define rlMX21_FIPNDH		*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x60)
#define rlMX21_FIPNDL		*(volatile unsigned long*)(DMX21_REG_AITC_BASE+0x64)



/*
 * PLL Clock
 */
#define DMX21_REG_PLL_BASE		0x10027000
#define rlMX21_CSCR			*(volatile unsigned long*)(DMX21_REG_PLL_BASE+0x00)
#define rlMX21_MPCTL0		*(volatile unsigned long*)(DMX21_REG_PLL_BASE+0x04)
#define rlMX21_MPCTL1		*(volatile unsigned long*)(DMX21_REG_PLL_BASE+0x08)
#define rlMX21_SPCTL0		*(volatile unsigned long*)(DMX21_REG_PLL_BASE+0x0C)
#define rlMX21_SPCTL1		*(volatile unsigned long*)(DMX21_REG_PLL_BASE+0x10)
#define rlMX21_OSC26MCTL	*(volatile unsigned long*)(DMX21_REG_PLL_BASE+0x14)
#define rlMX21_PCDR0		*(volatile unsigned long*)(DMX21_REG_PLL_BASE+0x18)
#define rlMX21_PCDR1		*(volatile unsigned long*)(DMX21_REG_PLL_BASE+0x1C)
#define rlMX21_PCCR0		*(volatile unsigned long*)(DMX21_REG_PLL_BASE+0x20)
#define rlMX21_PCCR1		*(volatile unsigned long*)(DMX21_REG_PLL_BASE+0x24)
#define rlMX21_CCSR			*(volatile unsigned long*)(DMX21_REG_PLL_BASE+0x28)
#define rlMX21_PMCTL		*(volatile unsigned long*)(DMX21_REG_PLL_BASE+0x2C)
#define rlMX21_PMCOUNT		*(volatile unsigned long*)(DMX21_REG_PLL_BASE+0x30)
#define rlMX21_WKGDCTL		*(volatile unsigned long*)(DMX21_REG_PLL_BASE+0x34)


/*
 * Watchdog Timer Control
 */
#define DMX21_REG_WDTC_BASE    0x10002000
#define rsMX21_WCR         *(volatile unsigned short*)(DMX21_REG_WDTC_BASE+0x00)
#define rsMX21_WSR         *(volatile unsigned short*)(DMX21_REG_WDTC_BASE+0x02)
#define rsMX21_WRSR        *(volatile unsigned short*)(DMX21_REG_WDTC_BASE+0x04)


/*
 * Real Time Clock Module
 */
#define DMX21_REG_RTC_BASE     0x10007000
#define rlMX21_DAYR        *(volatile unsigned long*)(DMX21_REG_RTC_BASE+0x20)
#define rlMX21_HOURMIN     *(volatile unsigned long*)(DMX21_REG_RTC_BASE+0x00)
#define rlMX21_SECONDS     *(volatile unsigned long*)(DMX21_REG_RTC_BASE+0x04)
#define rlMX21_DAYALARM    *(volatile unsigned long*)(DMX21_REG_RTC_BASE+0x24)
#define rlMX21_ALRM_HM     *(volatile unsigned long*)(DMX21_REG_RTC_BASE+0x08)
#define rlMX21_ALRM_SEC    *(volatile unsigned long*)(DMX21_REG_RTC_BASE+0x0C)
#define rlMX21_RCCTL       *(volatile unsigned long*)(DMX21_REG_RTC_BASE+0x10)
#define rlMX21_RTCISR      *(volatile unsigned long*)(DMX21_REG_RTC_BASE+0x14)
#define rlMX21_RTCIENR     *(volatile unsigned long*)(DMX21_REG_RTC_BASE+0x18)
#define rlMX21_STPWCH      *(volatile unsigned long*)(DMX21_REG_RTC_BASE+0x1C)


/*
 * General-Purpose Timer
 */
#define DMX21_REG_GPT_BASE    	0x10003000
#define DMX21_REG_TCTL_BASE		(DMX21_REG_GPT_BASE+0x00)
#define DMX21_REG_TPRER_BASE	(DMX21_REG_GPT_BASE+0x04)
#define DMX21_REG_TCMP_BASE		(DMX21_REG_GPT_BASE+0x08)
#define DMX21_REG_TCR_BASE		(DMX21_REG_GPT_BASE+0x0C)
#define DMX21_REG_TCN_BASE		(DMX21_REG_GPT_BASE+0x10)
#define DMX21_REG_TSTAT_BASE	(DMX21_REG_GPT_BASE+0x14)

#define DMX21_REG_GPT1_OFFSET	0x00000000
#define DMX21_REG_GPT2_OFFSET	0x00001000
#define DMX21_REG_GPT3_OFFSET   0x00002000


/*
 * General-Purpose I/O (GPIO)
 */

#define DMX21_REG_GPIO_BASE        0x10015000
#define DMX21_REG_DDIR_BASE        (DMX21_REG_GPIO_BASE+0x00)
#define DMX21_REG_OCR1_BASE        (DMX21_REG_GPIO_BASE+0x04)
#define DMX21_REG_OCR2_BASE        (DMX21_REG_GPIO_BASE+0x08)
#define DMX21_REG_ICONFA1_BASE     (DMX21_REG_GPIO_BASE+0x0C)
#define DMX21_REG_ICONFA2_BASE     (DMX21_REG_GPIO_BASE+0x10)
#define DMX21_REG_ICONFB1_BASE     (DMX21_REG_GPIO_BASE+0x14)
#define DMX21_REG_ICONFB2_BASE     (DMX21_REG_GPIO_BASE+0x18)
#define DMX21_REG_DR_BASE          (DMX21_REG_GPIO_BASE+0x1C)
#define DMX21_REG_GUIS_BASE        (DMX21_REG_GPIO_BASE+0x20)
#define DMX21_REG_SSR_BASE         (DMX21_REG_GPIO_BASE+0x24)
#define DMX21_REG_ICR1_BASE        (DMX21_REG_GPIO_BASE+0x28)
#define DMX21_REG_ICR2_BASE        (DMX21_REG_GPIO_BASE+0x2C)
#define DMX21_REG_IMR_BASE         (DMX21_REG_GPIO_BASE+0x30)
#define DMX21_REG_ISR_BASE         (DMX21_REG_GPIO_BASE+0x34)
#define DMX21_REG_GPR_BASE         (DMX21_REG_GPIO_BASE+0x38)
#define DMX21_REG_SWR_BASE         (DMX21_REG_GPIO_BASE+0x3C)
#define DMX21_REG_PUEN_BASE        (DMX21_REG_GPIO_BASE+0x40)
#define DMX21_REG_PMASK_BASE       (DMX21_REG_GPIO_BASE+0x60)

#define rlMX21_PTA_DDIR            *(volatile unsigned long*)(DMX21_REG_DDIR_BASE+0x000)
#define rlMX21_PTB_DDIR            *(volatile unsigned long*)(DMX21_REG_DDIR_BASE+0x100)
#define rlMX21_PTC_DDIR            *(volatile unsigned long*)(DMX21_REG_DDIR_BASE+0x200)
#define rlMX21_PTD_DDIR            *(volatile unsigned long*)(DMX21_REG_DDIR_BASE+0x300)
#define rlMX21_PTE_DDIR            *(volatile unsigned long*)(DMX21_REG_DDIR_BASE+0x400)
#define rlMX21_PTF_DDIR            *(volatile unsigned long*)(DMX21_REG_DDIR_BASE+0x500)
#define rlMX21_PTA_OCR1            *(volatile unsigned long*)(DMX21_REG_OCR1_BASE+0x000)