📄 sub_reset_lcd_controller.s
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;START_HEADER
;
; dsPIC30F6014 Demo Source File
; (c) Copyright 2005 Microchip Technology, All rights reserved
;
; --------------------------------------------------------------------------
; File Revision History:
; --------------------------------------------------------------------------
;
; $Log: sub_reset_lcd_controller.s,v $
; Revision 1.1 2006/07/07 15:32:10 c13075
; initial rev
;
; Revision 1.3 2005/04/04 23:38:25 VasukiH
; Updated comments in header
;
; Revision 1.2 2005/04/04 23:13:54 VasukiH
; Updates for MPLAB C30 v1.30 compatiblity
;
; Revision 1.1.1.1 2003/08/23 00:38:33 VasukiH
; First import of demo source into CVS Repository
;
;
;
; --------------------------------------------------------------------------
;
; Software and Development Tools Info:
; --------------------------------------------------------------------------
; Tool Version
; --------------------------------------------------------------------------
; MPLAB IDE 7.0
; MPLAB C30 Toolsuite 1.30
; dsPICDEM(TM) Processor Board 1.10
; --------------------------------------------------------------------------
;
; File Notes:
; 1. This subroutine will reset the LCD controller and provide a power-up
; time delay so that the dsPIC does not communicate to the LCD controller
; before the LCD controller has fully powered up. The time delay provided
; is ~250milliseconds which should be more than enough to ensure the LCD
; has power-up fully.
;
;END_HEADER
.include "p30fxxxx.inc"
.global _sub_reset_lcd_controller
_sub_reset_lcd_controller:
push.d w0
;Ensure LCD Controller is up and running
mov #256, w0
mov #7080, w1
do w1, end_delay1
repeat w0
nop
nop
end_delay1:
nop
;Reset LCD Controller
bclr SPI2STAT, #SPIROV ;Clear overflow flag
bset LATG, #LATG9 ;Deselect Slave LCD controller
bclr LATG, #LATG9 ;Select Slave LCD controller
mov.b SPI2BUF, WREG
mov.b #0x80, w0
mov.b WREG, SPI2BUF
poll_port:
btss SPI2STAT, #SPIRBF
bra poll_port
mov.b SPI2BUF, WREG
;Ensure LCD Controller is up and running again
mov #256, w0
mov #7080, w1
do w1, end_delay2
repeat w0
nop
nop
end_delay2:
nop
;Enable SPI Interrupt Processing
bset IEC1, #SPI2IE ; Enable SPI2 ISR processing
pop.d w0
return
.end ;EOF
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