vpx.txt

huffman编码压缩

VPX and VPX-REDI standards enables next-generation applications

Next-generation embedded applications need quantities of backplane I/O and bandwidth that is simply not available from traditional VME. Traditional VME64x is limited by its bandwidth, currently 320 MB/s and its backplane I/O, provided by the P0 and P2 connectors, offers only 205 user pins.While VME will continue to deliver sufficient compute performance for numerous embedded applications, the next generation of defense and aerospace applications will increasingly demand ever higher performance and support for distributed multiprocessing architectures based on serial switched fabrics such as Serial RapidIO and Advanced Switching Interconnect.

In response to the burgeoning performance requirements of emerging military COTS applications, member companies of the VME International Trade Association (VITA) have developed the new VITA 46 (VPX) standard.VPX provides significantly greater numbers of I/O pins and boosts bandwidth support up to 30 GB/s. Even better, VPX adds support for ESD covers to address the military’s goal of achieving 2-level maintenance for in-the-field replacement of modules. To support higher levels of functional density on the 6U form factor, VPX features improved power provisioning. VME was limited to 90 W at 5 V. In comparison, VPX provides options for up to 115 W at 5 V power, 384 W at 12 V power, and up to 768W at 48V.While the VPX standard looks forward, it also ensures backwards compatibility with the existing VME system ecosystem. It supports familiar aspects of VME, including the 6U format, support for standard-length PMC and XMC modules, 5 V power inputs, and the option for a standard VMEbus electrical interface. To protect customer investment in existing hardware, hybrid chassis have been developed to house both VPX and VME modules.

The VPX standard, which defines both 6U and 3U modules, is targeted for emerging highspeed I/O standards such as high-resolution digital video, storage interfaces, and multi-gigabit/s networking technologies.When used with VPX, modern industry-standard serial switched fabrics, such as Serial RapidIO and Advanced Switching Interconnect, can deliver data rates of 250 MB/s per differential pair – or up to 1 GB/s over a 4-lane port. Through provisioning for 32 differential pairs of core fabric, organized as 4 ports of 4 lanes each (bidirectional), the nominal aggregate backplane bandwidth of a VPX module is 8 GB/s. To achieve this leap in bandwidth, VPX replaces the standard VME backplane connector with a new connector, the MultiGig RT-2, developed by Tyco. The RT-2 has a wafer-style design that features tightly controlled impedance, low insertion loss, and less than 3% crosstalk at edge rates of 50 ps, allowing it to handle signalling rates up to 6.25 Gbit/s. The new connector has a series of 7-contact (also referred to as “7-row”) wafers, which are available in three different types: differential pairs rated to 6.25 Gbit/s, single-ended, and power. Figure 1 shows a representative VPX-format module.

Besides providing excellent signal integrity for high-speed signals, the 7-row MultiGig RT-2 connector offers other important characteristics including: the size of the connector is such that it can be mounted on a standard 3U or 6U x 160 mm card size and still allows a standardlength PMC or XMC (VITA 42) to be hosted; the connector functions reliably in high shock and vibration environments, as has been demonstrated by the connector and module test program conducted by the VITA 46 Working Group and documented in a detailed report available from the VITA web site,www.vita.com; the connector provides an integral mechanism to protect the signal contacts from ESD discharge. Figure 2 shows the daughter-card half of the 7-row MultiGig RT-2 connector. The integrated ESD protection mentioned above is provided by ground strips located on the leading

edge of the backside of the signal wavers. This ESD protection enables support for 2-level maintenance – an emerging requirement for new military deployed computing systems targeted to reduce the overall life-cycle cost of a system. 2-Level maintenance makes module-level replacement practical, and compared to field replacement of subsystem-level components, it significantly reduces sparing and logistics requirements, lowering the total life-cycle cost of the systems in which the VPX boards are deployed. Since VME was first introduced, the VSO (VITA Standards Organization) has made several performance enhancements to the open standard bus. The first of these was 64-bit multiplexed block-level transfer (MBLT),which increased the speed of the VMEbus to a theoretical maximum of 80 MB/s. In 2003, VITA 1.5 2eSST, a high-performance synchronous protocol, was approved by the standards body. 2eSST enables VMEbus backplane transfers at 160 MB/s, 266 MB/s, and 320 MB/s and can be used with existing VME64x backplanes.

A more recent enhancement to traditional VME is VXS (VITA 41), a VME switch fabric serial backplane standard. VXS is backwardcompatible with legacy VME at the P1 and P2 DIN connector level. It diverges from legacy VME in its use of a fifteen wafer 7-row,Multi- Gig RT-2 P0 connector. This connector provides 68 signal pins (30 differential pairs at 2 per wafer). By replacing the 95-pin Metral P0 connector with the MultiGig RT2 connector, VXS takes high-speed differential signalling off the backplane.Compared to VPX,VXS has only 30 differential pairs and 95 fewer I/O pins than VME64x. This limits VXS users to two x4 ports out the back for centralized switching.

VPX, on the other hand, is one of two new standards recently developed to address demanding applications that require throughput greater than 320 MB/s (VME’s current limit with 2eSST) and to provide multi-processing and streaming I/O beyond the capability of VME’s parallel bus architecture. Like VPX, VXS (VITA 41) brings switched serial fabric support to the VME ecosystem.

VPX addresses the limitation of VXS by providing the bandwidth and pin-counts needed by customers who want distributed switching, and large amounts of streaming I/O while still maintaining access to low-speed discrete I/O. VPX, in a typical 6U configuration, provides 128 differential pairs for user I/O along with 12 single-ended contacts for a grand total of 268 user I/O signals, enough to amply support basecard I/O and I/O for PMC/XMC mezzanines. VPX also supports a full A32:D32 VME interface and 32 differential pairs allocated to thecore fabric. Figure 3 illustrates the backplane I/O provisions of the VPX standard.An important standard closely related to VPX is VPXREDI (ruggedized enhanced design implementation). VPX and VPX-REDI are being developed hand-in-hand.Whereas VPX focused on developing a new-generation backplane interconnection scheme compatible with traditional 3U and 6U mechanical arrangements, VPX-REDI focuses on innovative mechanical design techniques that enable new levels of computing density to be achieved in deployed military environments.

VPX-REDI defines a general mechanical design implementation for circuit card assemblies to expand the present implementations in the areas of 2-level maintenance, thermal management, structural ruggedization, and increasing the usable real-estate and volume on the secondary side of the PCB, and initially encompasses air-cooling, conduction-cooling, and liquid flow-through applications. Future extensions to cover other types of cooling such as wet- and dry-spray-cooling are anticipated. VPX-REDI is the first COTS standard to codify the implementation of cooling in the form of liquid flowing through the module’s cold plate from the backplane. Figure 4 illustrates a representative 6U VPX-REDI format module.

Curtiss-Wright’s recently announced CHAMPAV6 and VPX6-185 single-board computers are COTS boards to support 2-level in-the-field maintenance requirements. The 6U VPX6-185 features include a nominal backplane bandwidth of 8 GB/s via four Advanced Switching Interconnect (ASI) ports, two PCI Express VITA 42 XMC/PMC sites, the processing power of Freescale’s 8641 single/dual-core PowerPC processor, and an extensive list of standard features such as Gigabit Ethernet (GbE), serial ports, and mass storage interface options. The VPX6-185 features a Freescale 8641 single/dualcore PowerPC processing engine.With its dual integrated 64-bit memory controllers, the 8641 offers increased memory performance, translating directly to reduced execution times for user application software. For numeric-intense processing the 8641 offers the powerful Altivec instruction- set extension, which performs up to 8 floating-point operations per cycle. For a dual-core device operating at 1.5 GHz this results in 24 gigaflops of peak floating-point performance.

For core backplane connectivity the VPX6-185 incorporates four ASI switch ports. ASI is based on PCI Express and extends PCI Express with peer-to-peer message passing protocols to provide efficient, low-latency inter-processor communications. The VPX6-185's four ASI ports together provide a nominal 8 GB of backplane bandwidth, sufficient to handle challenging data throughput requirements such as multiple streams of sensor video or re-ceiver data. For integration with high-density
computing products such as Curtiss-Wrights CHAMP-AV6 VPX-based DSP engine, the VPX6-185 also provides Serial RapidIO connectivity. The dual XMC/PMC sites on the VPX6-185 conform to the VITA 42.3 standard and can accept either standard PMC modules or XMC modules, featuring PCI Express with automatic detection of the module type.With PCI Express connectivity, the two XMC sites provide the high bandwidth to memory required for high-performance graphics, networking, and data acquisition modules. By virtue of the increased I/O count of the VPX format, the XMC I/O connectors are provided with dedicated backplane I/O pins. The CHAMP-AV6 features four on-board 8641 single-core PowerPC devices.

With four 1.33 GHz 8641s, the CHAMP-AV6 delivers 42 gigaflops of peak floating-point performance.Multi-processor systems based on the CHAMP-AV6 will benefit from the 10 GB/s full-duplex bandwidth provided by the board’s four Serial RapidIO ports; this represents a data throughput rate approximately 10x faster than today’s best VME/StarFabric implementation. Streaming data applications will benefit from the board’s 8.5 GB/s memory bandwidth and up to 2 GB of DDR-II SDRAM. Software for the CHAMP-AV6 includes support for operating systems including VxWorks, Linux, and Gedae. Curtiss-Wright provides signal processing libraries and a high-performance Inter- Processor Communications Library for message passing and bulk data transfers, extending to multiple boards connected via Serial RapidIO.