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📄 ml505.8

📁 xilinx 公司的ML150系列开发板的电路图
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I 773 dxdesigner_lib:RES 1 420 390 3 1 '
|R 15:52_10-14-05
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|R 15:54_10-14-05
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|R 23:22_2-6-06
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I 693 dxdesigner_lib:M25P80 1 1390 380 0 1 '
|R 23:40_3-7-06
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I 576 dxdesigner_lib:CPACK-4 1 110 840 1 1 '
|R 20:06_10-11-05
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I 574 dxdesigner_lib:CPACK-4 1 200 840 1 1 '
|R 20:06_10-11-05
A 155 850 10 1 3 3 REFDES=CP11
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I 579 dxdesigner_lib:CAP_NP 1 1240 990 0 1 '
|R 17:04_10-27-05
A 1240 880 10 0 3 0 DXDB_LIBNAME=CAPACITORS
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A 1240 950 10 0 3 0 DATASHEET=\\FENPHEN\AFX\AFX\BOARD_PROJECTS\LIBRARY\\DATASHEE
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A 1240 960 10 0 3 0 PKG_TYPE=0402
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I 724 dxdesigner_lib:RES 1 390 570 3 1 '
|R 15:52_10-14-05
A 290 570 10 3 3 0 DXDB_LIBNAME=RESISTORS
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I 622 dxdesigner_lib:RES 1 1350 825 0 1 '
|R 15:52_10-14-05
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I 523 dxdesigner_lib:GND 1 501 730 0 1 '
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I 807 dxdesigner_lib:RES 1 350 990 0 1 '
|R 15:52_10-14-05
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|R 22:50_2-28-06
C 528 1 2 0
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|R 15:52_10-14-05
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|R 15:54_10-14-05
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A 345 680 9 1 2 0 POWER=1/16W
A 370 670 9 1 2 3 VALUE=0
A 345 670 10 1 3 0 PART_TYPE=SMT - 5%
A 349 670 9 1 2 3 REFDES=R49
C 802 1 1 0
A 365 705 9 2 3 3 #=2
C 803 1 2 0
A 365 675 9 2 3 3 #=1
I 3 schematics:BSHEETL 1 1260 0 0 1 '
T 1350 110 10 0 3 0381241
T 1350 130 10 0 3 SCHEM, ROHS COMPLIANT
T 1570 795 6 0 3 1
c 1590 790 5
b 1580 780 1600 800
b 1580 740 1600 760
b 1580 720 1600 740
b 1580 760 1600 780
b 1580 700 1600 720
c 1590 670 5
T 1605 745 10 0 3 TDI
T 1605 725 10 0 3 TDO
T 1605 705 10 0 3 TCK
T 1605 685 10 0 3 GND
T 1605 665 10 0 3 VCC3V3
c 1590 690 5
c 1590 710 5
c 1590 730 5
c 1590 750 5
c 1590 770 5
T 480 205 10 0 3 SysACE Config, Mode pins
T 1500 670 10 0 3 VCC3V3
T 1500 690 10 0 3 GND
T 1500 710 10 0 3 TCK
T 1500 730 10 0 3 TDO
T 1500 750 10 0 3 TDI
T 460 215 10 0 3 Silkscreen:
b 1580 660 1600 680
b 1580 680 1600 700
T 1605 765 10 0 3 TMS
T 1260 250 20 0 3 Misc Config
T 1280 230 20 0 3 Platform Flash,
T 1280 210 20 0 3 SPI Flash
T 1530 820 10 0 3 Silkscreen:
T 1415 835 20 0 3 SPI Program Header
T 1605 785 10 0 3 INIT
T 1500 770 10 0 3 TMS
T 1500 790 10 0 3 PROG_B
T 1590 810 10 0 6 SPI Prog
T 560 65 10 0 6 Config DIP switches
T 865 65 10 0 6 Toggles connection from Plat Flash D0 to SRAM D0
T 1365 545 20 0 3 SPI Flash
T 695 1005 20 0 6 Platform Flash #1
T 695 635 20 0 6 Platform Flash #2
T 435 355 10 0 6 Populate to Bypass
T 435 345 10 0 6 Plat Flash #2
T 1420 140 10 0 3 Platform Flash, SPI Flash
T 1350 140 10 0 3 Misc Config,
U 1610 40 10 0 3 3 SCHEMDRAWN=BP
U 1560 70 10 0 3 3 SCHEMREV=02
U 1473 94 10 0 9 3 @DATETIME=1-22-2008_14:51
U 1483 34 30 0 9 3 @SHEETTOTAL=27
U 1383 34 30 0 9 3 @SHEET=8
U 1560 90 10 0 3 3 SCHEMVER=A
T 1350 120 10 0 3 ML505/6/7 VIRTEX-5 EVALUATION PLATFORM, 1280415
E

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