hal_uart.s51

用IAR开发的ZIGBEE网络路由例子

        ARGFRAME XSTACK, 14, STACK

// C:\Texas Instruments\ZStack-1.4.2\Components\hal\target\CC2430DB\hal_uart.c
//    1 /******************************************************************************
//    2     Filename:       _hal_uart.c
//    3     Revised:        $Date: 2007-03-26 11:53:55 -0700 (Mon, 26 Mar 2007) $
//    4     Revision:       $Revision: 13853 $
//    5 
//    6     Description: This file contains the interface to the H/W UART driver.
//    7 
//    8     Copyright (c) 2007 by Texas Instruments, Inc.
//    9     All Rights Reserved.  Permission to use, reproduce, copy, prepare
//   10     derivative works, modify, distribute, perform, display or sell this
//   11     software and/or its documentation for any purpose is prohibited
//   12     without the express written consent of Texas Instruments, Inc.
//   13 ******************************************************************************/
//   14 
//   15 /*********************************************************************
//   16  * INCLUDES
//   17  */
//   18 
//   19 #include "hal_types.h"
//   20 #include "hal_assert.h"
//   21 #include "hal_board.h"

        ASEGN SFR_AN:DATA:NOROOT,095H
// unsigned char volatile __sfr ST0
ST0:
        DS 1

        ASEGN SFR_AN:DATA:NOROOT,09aH
// unsigned char volatile __sfr IEN2
IEN2:
        DS 1

        ASEGN SFR_AN:DATA:NOROOT,0c1H
// unsigned char volatile __sfr U0DBUF
U0DBUF:
        DS 1

        ASEGN SFR_AN:DATA:NOROOT,0f1H
// unsigned char volatile __sfr PERCFG
PERCFG:
        DS 1

        ASEGN SFR_AN:DATA:NOROOT,0f2H
// unsigned char volatile __sfr ADCCFG
ADCCFG:
        DS 1

        ASEGN SFR_AN:DATA:NOROOT,0f4H
// unsigned char volatile __sfr P1SEL
P1SEL:
        DS 1

        ASEGN SFR_AN:DATA:NOROOT,0f9H
// unsigned char volatile __sfr U1DBUF
U1DBUF:
        DS 1

        ASEGN SFR_AN:DATA:NOROOT,0faH
// unsigned char volatile __sfr U1BAUD
U1BAUD:
        DS 1

        ASEGN SFR_AN:DATA:NOROOT,0fbH
// unsigned char volatile __sfr U1UCR
U1UCR:
        DS 1

        ASEGN SFR_AN:DATA:NOROOT,0fcH
// unsigned char volatile __sfr U1GCR
U1GCR:
        DS 1

        ASEGN SFR_AN:DATA:NOROOT,0feH
// unsigned char volatile __sfr P1DIR
P1DIR:
        DS 1

        ASEGN SFR_AN:DATA:NOROOT,0ffH
// unsigned char volatile __sfr P2DIR
P2DIR:
        DS 1
//   22 #include "hal_defs.h"
//   23 #if defined( HAL_UART_DMA ) && HAL_UART_DMA
//   24   #include "hal_dma.h"
//   25 #endif
//   26 #include "hal_mcu.h"
//   27 #include "hal_uart.h"
//   28 #include "osal.h"
//   29 
//   30 /*********************************************************************
//   31  * MACROS
//   32  */
//   33 
//   34 #if !defined ( HAL_UART_DEBUG )
//   35   #define HAL_UART_DEBUG  FALSE
//   36 #endif
//   37 
//   38 #if !defined ( HAL_UART_CLOSE )
//   39   #define HAL_UART_CLOSE  FALSE
//   40 #endif
//   41 
//   42 #if !defined ( HAL_UART_BIG_TX_BUF )
//   43   #define HAL_UART_BIG_TX_BUF  FALSE
//   44 #endif
//   45 
//   46 /*
//   47  *  The MAC_ASSERT macro is for use during debugging.
//   48  *  The given expression must evaluate as "true" or else fatal error occurs.
//   49  *  At that point, the call stack feature of the debugger can pinpoint where
//   50  *  the problem occurred.
//   51  *
//   52  *  To disable this feature and save code size, the project should define
//   53  *  HAL_UART_DEBUG to FALSE.
//   54  */
//   55 #if ( HAL_UART_DEBUG )
//   56   #define HAL_UART_ASSERT( expr)        HAL_ASSERT( expr )
//   57 #else
//   58   #define HAL_UART_ASSERT( expr )
//   59 #endif
//   60 
//   61 #define P2DIR_PRIPO               0xC0
//   62 #if HAL_UART_0_ENABLE
//   63   #define HAL_UART_PRIPO          0x00
//   64 #else
//   65   #define HAL_UART_PRIPO          0x40
//   66 #endif
//   67 
//   68 #define HAL_UART_0_PERCFG_BIT     0x01  // USART0 on P0, so clear this bit.
//   69 #define HAL_UART_0_P0_RX_TX       0x0c  // Peripheral I/O Select for Rx/Tx.
//   70 #define HAL_UART_0_P0_RTS         0x10  // Peripheral I/O Select for RTS.
//   71 #define HAL_UART_0_P0_CTS         0x20  // Peripheral I/O Select for CTS.
//   72 
//   73 #define HAL_UART_1_PERCFG_BIT     0x02  // USART1 on P1, so set this bit.
//   74 #define HAL_UART_1_P1_RTS         0x10  // Peripheral I/O Select for RTS.
//   75 #define HAL_UART_1_P1_CTS         0x20  // Peripheral I/O Select for CTS.
//   76 #define HAL_UART_1_P1_RX_TX       0xC0  // Peripheral I/O Select for Rx/Tx.
//   77 
//   78 #define TX_AVAIL( cfg ) \ 
//   79   ((cfg->txTail == cfg->txHead) ? (cfg->txMax-1) : \ 
//   80   ((cfg->txTail >  cfg->txHead) ? (cfg->txTail - cfg->txHead - 1) : \ 
//   81                      (cfg->txMax - cfg->txHead + cfg->txTail)))
//   82 
//   83 #define RX0_FLOW_ON  ( P0 &= ~HAL_UART_0_P0_CTS )
//   84 #define RX0_FLOW_OFF ( P0 |= HAL_UART_0_P0_CTS )
//   85 #define RX1_FLOW_ON  ( P1 &= ~HAL_UART_1_P1_CTS)
//   86 #define RX1_FLOW_OFF ( P1 |= HAL_UART_1_P1_CTS )
//   87 
//   88 #define RX_STOP_FLOW( cfg ) { \ 
//   89   if ( !(cfg->flag & UART_CFG_U1F) ) \ 
//   90   { \ 
//   91     RX0_FLOW_OFF; \ 
//   92   } \ 
//   93   else \ 
//   94   { \ 
//   95     RX1_FLOW_OFF; \ 
//   96   } \ 
//   97   if ( cfg->flag & UART_CFG_DMA ) \ 
//   98   { \ 
//   99     cfg->rxTick = DMA_RX_DLY; \ 
//  100   } \ 
//  101   cfg->flag |= UART_CFG_RXF; \ 
//  102 }
//  103 
//  104 #define RX_STRT_FLOW( cfg ) { \ 
//  105   if ( !(cfg->flag & UART_CFG_U1F) ) \ 
//  106   { \ 
//  107     RX0_FLOW_ON; \ 
//  108   } \ 
//  109   else \ 
//  110   { \ 
//  111     RX1_FLOW_ON; \ 
//  112   } \ 
//  113   cfg->flag &= ~UART_CFG_RXF; \ 
//  114 }
//  115 
//  116 #define UART_RX_AVAIL( cfg ) \ 
//  117   ( (cfg->rxHead >= cfg->rxTail) ? (cfg->rxHead - cfg->rxTail) : \ 
//  118                                    (cfg->rxMax - cfg->rxTail + cfg->rxHead +1 ) )
//  119 
//  120 /* Need to leave enough of the Rx buffer free to handle the incoming bytes
//  121  * after asserting flow control, but before the transmitter has obeyed it.
//  122  * At the max expected baud rate of 115.2k, 16 bytes will only take ~1.3 msecs,
//  123  * but at the min expected baud rate of 38.4k, they could take ~4.2 msecs.
//  124  * SAFE_RX_MIN and DMA_RX_DLY must both be consistent according to
//  125  * the min & max expected baud rate.
//  126  */
//  127 #if !defined( SAFE_RX_MIN )
//  128   #define SAFE_RX_MIN  48  // bytes - max expected per poll @ 115.2k
//  129   // 16 bytes @ 38.4 kBaud -> 4.16 msecs -> 138 32-kHz ticks.
//  130   #define DMA_RX_DLY  140
//  131   //  2 bytes @ 38.4 kBaud -> 0.52 msecs ->  17 32-kHz ticks.
//  132   #define DMA_TX_DLY   20
//  133 #endif
//  134 
//  135 // The timeout tick is at 32-kHz, so multiply msecs by 33.
//  136 #define RX_MSECS_TO_TICKS  33
//  137 
//  138 // The timeout only supports 1 byte.
//  139 #if !defined( HAL_UART_RX_IDLE )
//  140   #define HAL_UART_RX_IDLE  (6 * RX_MSECS_TO_TICKS)
//  141 #endif
//  142 
//  143 // Only supporting 1 of the 2 USART modules to be driven by DMA at a time.
//  144 #if HAL_UART_DMA == 1
//  145   #define DMATRIG_RX  HAL_DMA_TRIG_URX0
//  146   #define DMATRIG_TX  HAL_DMA_TRIG_UTX0
//  147   #define DMA_UDBUF   HAL_DMA_U0DBUF
//  148   #define DMA_PAD     U0BAUD
//  149 #elif HAL_UART_DMA == 2
//  150   #define DMATRIG_RX  HAL_DMA_TRIG_URX1
//  151   #define DMATRIG_TX  HAL_DMA_TRIG_UTX1
//  152   #define DMA_UDBUF   HAL_DMA_U1DBUF
//  153   #define DMA_PAD     U1BAUD
//  154 #endif
//  155 
//  156 #define DMA_RX( cfg ) { \ 
//  157   volatile uint8 ft2430 = U0DBUF; \ 
//  158   \ 
//  159   halDMADesc_t *ch = HAL_DMA_GET_DESC1234( HAL_DMA_CH_RX ); \ 
//  160   \ 
//  161   HAL_DMA_SET_DEST( ch, cfg->rxBuf ); \ 
//  162   \ 
//  163   HAL_DMA_SET_LEN( ch, cfg->rxMax ); \ 
//  164   \ 
//  165   HAL_DMA_CLEAR_IRQ( HAL_DMA_CH_RX ); \ 
//  166   \ 
//  167   HAL_DMA_ARM_CH( HAL_DMA_CH_RX ); \ 
//  168 }
//  169 
//  170 #define DMA_TX( cfg ) { \ 
//  171   halDMADesc_t *ch = HAL_DMA_GET_DESC1234( HAL_DMA_CH_TX ); \ 
//  172   \ 
//  173   HAL_DMA_SET_SOURCE( ch, (cfg->txBuf + cfg->txTail) ); \ 
//  174   \ 
//  175   HAL_DMA_SET_LEN( ch, cfg->txCnt ); \ 
//  176   \ 
//  177   HAL_DMA_CLEAR_IRQ( HAL_DMA_CH_TX ); \ 
//  178   \ 
//  179   HAL_DMA_ARM_CH( HAL_DMA_CH_TX ); \ 
//  180   \ 
//  181   HAL_DMA_START_CH( HAL_DMA_CH_TX ); \ 
//  182 }
//  183 
//  184 /*********************************************************************
//  185  * TYPEDEFS
//  186  */
//  187 
//  188 typedef struct
//  189 {
//  190   uint8 *rxBuf;
//  191   uint8 rxHead;
//  192   uint8 rxTail;
//  193   uint8 rxMax;
//  194   uint8 rxCnt;
//  195   uint8 rxTick;
//  196   uint8 rxHigh;
//  197 
//  198   uint8 *txBuf;
//  199 #if HAL_UART_BIG_TX_BUF
//  200   uint16 txHead;
//  201   uint16 txTail;
//  202   uint16 txMax;
//  203   uint16 txCnt;
//  204 #else
//  205   uint8 txHead;
//  206   uint8 txTail;
//  207   uint8 txMax;
//  208   uint8 txCnt;
//  209 #endif
//  210   uint8 txTick;
//  211 
//  212   uint8 flag;
//  213 
//  214   halUARTCBack_t rxCB;
//  215 } uartCfg_t;
//  216 
//  217 /*********************************************************************
//  218  * CONSTANTS
//  219  */
//  220 
//  221 // Used by DMA macros to shift 1 to create a mask for DMA registers.
//  222 #define HAL_DMA_CH_TX    3
//  223 #define HAL_DMA_CH_RX    4
//  224 
//  225 #define HAL_DMA_U0DBUF  0xDFC1
//  226 #define HAL_DMA_U1DBUF  0xDFF9
//  227 
//  228 // UxCSR - USART Control and Status Register.
//  229 #define CSR_MODE      0x80
//  230 #define CSR_RE        0x40
//  231 #define CSR_SLAVE     0x20
//  232 #define CSR_FE        0x10
//  233 #define CSR_ERR       0x08
//  234 #define CSR_RX_BYTE   0x04
//  235 #define CSR_TX_BYTE   0x02
//  236 #define CSR_ACTIVE    0x01
//  237 
//  238 // UxUCR - USART UART Control Register.
//  239 #define UCR_FLUSH     0x80
//  240 #define UCR_FLOW      0x40
//  241 #define UCR_D9        0x20
//  242 #define UCR_BIT9      0x10
//  243 #define UCR_PARITY    0x08
//  244 #define UCR_SPB       0x04
//  245 #define UCR_STOP      0x02
//  246 #define UCR_START     0x01
//  247 
//  248 #define UTX0IE        0x04
//  249 #define UTX1IE        0x08
//  250 
//  251 #define UART_CFG_U1F  0x80  // USART1 flag bit.
//  252 #define UART_CFG_DMA  0x40  // Port is using DMA.
//  253 #define UART_CFG_FLW  0x20  // Port is using flow control.
//  254 #define UART_CFG_SP4  0x10
//  255 #define UART_CFG_SP3  0x08
//  256 #define UART_CFG_SP2  0x04
//  257 #define UART_CFG_RXF  0x02  // Rx flow is disabled.
//  258 #define UART_CFG_TXF  0x01  // Tx is in process.
//  259 
//  260 /*********************************************************************
//  261  * GLOBAL VARIABLES
//  262  */
//  263 
//  264 /*********************************************************************
//  265  * GLOBAL FUNCTIONS
//  266  */
//  267 
//  268 /*********************************************************************
//  269  * LOCAL VARIABLES
//  270  */
//  271 
//  272 #if HAL_UART_0_ENABLE
//  273 static uartCfg_t *cfg0;
//  274 #endif
//  275 #if HAL_UART_1_ENABLE

        RSEG XDATA_Z:XDATA:NOROOT(0)
        REQUIRE __INIT_XDATA_Z
//  276 static uartCfg_t *cfg1;
??cfg1:
        DS 2
//  277 #endif
//  278 
//  279 /*********************************************************************
//  280  * LOCAL FUNCTIONS