📄 led_test.map.rpt
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Analysis & Synthesis report for led_test
Wed Nov 19 09:36:20 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Analysis & Synthesis RAM Summary
8. State Machine - |led_test|first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize
9. Registers Protected by Synthesis
10. Registers Removed During Synthesis
11. Removed Registers Triggering Further Register Optimizations
12. General Register Statistics
13. Inverted Register Statistics
14. Multiplexer Restructuring Statistics (Restructuring Performed)
15. Source assignments for first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_uob1:auto_generated
16. Source assignments for first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_uob1:auto_generated|altsyncram_6sk1:altsyncram1
17. Source assignments for first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_phe1:auto_generated
18. Source assignments for first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_4be1:auto_generated
19. Source assignments for first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_5be1:auto_generated
20. Source assignments for first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_c572:auto_generated
21. Source assignments for first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated
22. Source assignments for first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1
23. Source assignments for first_nios2_system:inst|onchip_RAM:the_onchip_RAM|altsyncram:the_altsyncram|altsyncram_oeb1:auto_generated
24. Source assignments for first_nios2_system:inst|onchip_ROM:the_onchip_ROM|altsyncram:the_altsyncram|altsyncram_teb1:auto_generated
25. Source assignments for first_nios2_system:inst|first_nios2_system_reset_clk_domain_synch_module:first_nios2_system_reset_clk_domain_synch
26. Source assignments for sld_hub:sld_hub_inst
27. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
28. Parameter Settings for User Entity Instance: first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data
29. Parameter Settings for User Entity Instance: first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram
30. Parameter Settings for User Entity Instance: first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag
31. Parameter Settings for User Entity Instance: first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram
32. Parameter Settings for User Entity Instance: first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a
33. Parameter Settings for User Entity Instance: first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram
34. Parameter Settings for User Entity Instance: first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b
35. Parameter Settings for User Entity Instance: first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram
36. Parameter Settings for User Entity Instance: first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component
37. Parameter Settings for User Entity Instance: first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram
38. Parameter Settings for User Entity Instance: first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component
39. Parameter Settings for User Entity Instance: first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram
40. Parameter Settings for User Entity Instance: first_nios2_system:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1
41. Parameter Settings for User Entity Instance: first_nios2_system:inst|onchip_RAM:the_onchip_RAM|altsyncram:the_altsyncram
42. Parameter Settings for User Entity Instance: first_nios2_system:inst|onchip_ROM:the_onchip_ROM|altsyncram:the_altsyncram
43. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
44. Analysis & Synthesis Messages
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; Legal Notice ;
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Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
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