armisr.h

s3c44b0实现中断控制。已通过调试。

#ifndef _ARM_ISR_H_
#define _ARM_ISR_H_


#define IRQBASE       (0x0C000100)
#define IRQVECTOR(x)  (IRQBASE + ((unsigned int)x)*4)

typedef enum {
  HandlerADC,
  HandlerRTC,
  HandlerUTXD1,
  HandlerUTXD0,
  HandlerSIO,
  HandlerIIC,
  HandlerURXD1,
  HandlerURXD0,
  HandlerTIMER5,
  HandlerTIMER4,
  HandlerTIMER3,
  HandlerTIMER2,
  HandlerTIMER1,
  HandlerTIMER0,
  HandlerUERR01,
  HandlerWDT   ,
  HandlerBDMA1 ,
  HandlerBDMA0 ,
  HandlerZDMA1 ,
  HandlerZDMA0 ,
  HandlerTICK  ,
  HandlerEINT4567,
  HandlerEINT3 ,
  HandlerEINT2 ,
  HandlerEINT1 ,
  HandlerEINT0 ,
  HandlerMax
} NON_VECTOR_HANDLER;


#endif