📄 f63reg.h
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#ifndef _F63REG_H
#define _F63REG_H
//----------------------------------------------------------
extern xdata unsigned char PortA; // (R/W) : $FF
extern xdata unsigned char PortB; // (R/W) : $FF
extern xdata unsigned char PortC; // (R/W) : $FF
extern xdata unsigned char PortD; // (R/W) : $FF
//--------------[ Watch-Dog Timer ]-------------------------
extern xdata unsigned char CLRWDT; // (-W-) : $55
//--------------[ A/D Converter ]---------------------------
extern xdata unsigned char ADC_CON; // (-W-) : $00
#define STRT_ADC 0x80 // Start A to D Convert
#define EN_ADC 0x10 // Enable ADC
#define EN_ADC3 0x08 // Enable ADC3
#define EN_ADC2 0x04 // Enable ADC2
#define EN_ADC1 0x02 // Enable ADC1
#define EN_ADC0 0x01 // Enable ADC0
extern xdata unsigned char ADC_REG[4]; // (-R-) : ADC0 Value
#define CMP_ADC 0x80 // (-R-): Complete ADC
//--------------[ PWM D/A Converters ]----------------------
extern xdata unsigned char ENPWM_LB; // (-W-) : Enable PWM07-PWM00
extern xdata unsigned char ENPWM_HB; // (-W-) : Enable PWM15-PWM08
extern xdata unsigned char PWM_REG[16];
//--------------[ DDC Port ]--------------------------------
extern xdata unsigned char DDC_CTRL;
#define EN_DDC 0x80
#define WPT_DDC 0x40
#define LEN_EDID 0x20
#define MODE_DDC 0x10
#define EN_BACK 0x08
#define INVT_VCLK 0x04
#define CLR_PTR 0x02
#define CLR_UPD 0x01
extern xdata unsigned char DDC_REG;
#define WR_SUCC 0x80
#define OVF_DDC 0x04
#define IS_CLRD 0x02
#define UPD_DDC 0x01
extern xdata unsigned char DDC_ADDR;
#define VALID_B31 0xe0
#define ADDRB_B31 0x0e
//--------------[ Signal Master I2C-Bus Port0 (on DDC Port) ]
extern xdata unsigned char INTIIC0_FLG;
#define INTA 0x10
#define INTTX 0x08
#define INTRX 0x04
#define INTNAK 0x02
#define INTSTOP 0x01
#define bINTA 4
#define bINTTX 3
#define bINTRX 2
#define bINTNAK 1
#define bINTSTOP 0
extern xdata unsigned char INTIIC0_EN;
#define INTA_EN 0x10
#define INTTX_EN 0x08
#define INTRX_EN 0x04
#define INTNAK_EN 0x02
#define INTSTOP_EN 0x01
extern xdata unsigned char IIC0_ADDR;
#define IIC_EN 0x01
extern xdata unsigned char IIC0_DATA;
extern xdata unsigned char IIC0_CON;
#define SRW 0x20
#define START 0x10
#define STOP 0x08
#define TXACK 0x02
extern xdata unsigned char IIC0_CLK;
#define MODE 0x80
#define MRW 0x40
#define RSTART 0x20
#define IIC_RB 0x07
//--------------[ Signal Master I2C-Bus Port1 (Intra Bus) ]
extern xdata unsigned char INTIIC1_FLG;
extern xdata unsigned char INTIIC1_EN;
extern xdata unsigned char IIC1_ADDR;
extern xdata unsigned char IIC1_DATA;
extern xdata unsigned char IIC1_CON;
extern xdata unsigned char IIC1_CLK;
//--------------[ Interrupt Sources ]-----------------------
extern xdata unsigned char INT_SRC;
#define INTUSB_IRQ 0x40
#define INTIIC0_IRQ 0x20
#define INTEXT_IRQ 0x10
#define INTIIC1_IRQ 0x02
#define INTHV_IRQ 0x01
#define bINTSUB_IRQ 6
#define bINTIIC0_IRQ 5
#define bINTEXT_IRQ 4
#define bINTIIC1_IRQ 1
#define bINTHV_IRQ 0
//--------------[ External Interrupt ]----------------------
extern xdata unsigned char INTEXT_FLG;
extern xdata unsigned char INTEXT_EN;
#define INTE1 0x02
#define INTE0 0x01
#define INTE1_EDG 0x20
#define INTE0_EDG 0x10
//--------------[ SyncProcessor ]---------------------------
extern xdata unsigned char INTHV_FLG;
extern xdata unsigned char INTHV_EN;
#define INT_H 0x80
#define INT_V 0x40
#define INT_HP 0x04
#define INT_VP 0x02
#define INT_FM 0x01 // 1: Enable Fast Mute
extern xdata unsigned char SYNC_REG;
#define EN_FRUN 0x80 // 1: Enable Free-Run Function
#define AUTO_FLT 0x40 // 1: Enable Auto Filter Function
#define EN_SOG 0x20 // 1: Enable SOG Function
#define EN_CLMP 0x10 // 1: Enable Clamp Function
#define EN_PAT 0x08 // 1: Enable Pattern Function
#define EN_HALF 0x04 // 1: Enable HALF Function
#define HALF_SEL 0x02 // 1: HALF_OUT = HALF_IN/2
#define HALF_POL 0x01
extern xdata unsigned char HVO_REG;
#define EN_HOUT 0x80 // 1: Enable HSYNCO Output Pin
#define EN_VOUT 0x40 // 1: Enable VSYNCO Output Pin
#define EN_HRUN 0x20 // 1: Enable Free-Run Horizontal output control
#define EN_VRUN 0x10 // 1: Enable Free-Run Vertical output control
#define EN_INS 0x08 // 1: Enable Insert pulse control
#define SYNCO_SEL 0x04 // 1: Sync outputs from the internal free running gererator
#define HO_POL 0x02
#define VO_POL 0x01
extern xdata unsigned char HVI_REG;
extern xdata unsigned char HPW_REG;
extern xdata unsigned char HFLT_REG;
extern xdata unsigned char CLMP_REG;
extern xdata unsigned char HVCNT_CTRL;
extern xdata unsigned char HCNT_LB;
extern xdata unsigned char HCNT_HB;
extern xdata unsigned char VCNT_LB;
extern xdata unsigned char VCNT_HB;
extern xdata unsigned char DCNT_LB;
extern xdata unsigned char DCNT_HB;
extern xdata unsigned char LCNT_LB;
extern xdata unsigned char LCNT_HB;
extern xdata unsigned char MUTE_CTRL;
//--------------[ Flash Memory ]----------------------------
extern xdata unsigned char ISP_REG;
#define ISP_FLG 0x02
#define ISP_CH 0x01
extern xdata unsigned char FLASH_BUF;
//--------------[ GPIO Directly Control ]-------------------
extern xdata unsigned char RDPA_REG;
extern xdata unsigned char RDPB_REG;
extern xdata unsigned char RDPC_REG;
extern xdata unsigned char RDPD_REG;
//--------------[ Stereo 3D Control ]-----------------------
extern xdata unsigned char S3D_REG;
#define EN_S3D 0x80
#define EN_LNKO 0x40
#define EN_IRO 0x20
#define EN_SSYNCO 0x10
#define SS_NOT 0x02
#define V3D_SEL 0x01
//--------------[ USB Port ]--------------------------------
extern xdata unsigned char IUSB2_FLG; // (R/W) : $00
#define R0_STL_FLG 0x80
#define T0_STL_FLG 0x40
#define RESMI 0x20
#define URST 0x10
#define NAK2 0x08
#define NAK11 0x04
#define NAKR0 0x02
#define NAKT0 0x01
extern xdata unsigned char IUSB2_EN; // (R/W) : $00
#define R0_STL_EN 0x80
#define T0_STL_EN 0x40
#define RESMI_EN 0x20
// #define URST 0x10
#define NAK2_EN 0x08
#define NAK11_EN 0x04
#define NAKR0_EN 0x02
#define NAKT0_EN 0x01
extern xdata unsigned char IUSB1_FLG; // (R/W) : $00
#define SUSP 0x80
#define STUP 0x40
#define OWSTUP 0x20
// #define RST 0x10
#define IN2 0x08
#define IN1 0x04
#define OT0 0x02
#define IN0 0x01
extern xdata unsigned char IUSB1_EN; // (R/W) : $00
#define SUSP_EN 0x80
#define STUP_EN 0x40
#define OWSTUP_EN 0x20
// #define RST_ 0x10
#define IN2_EN_EN 0x08
#define IN1_EN_EN 0x04
#define OT0_EN_EN 0x02
#define IN0_EN_EN 0x01
extern xdata unsigned char MODE_FG; // (R/W) : $02
extern xdata unsigned char USB_ADR; // (R/W) : $00
extern xdata unsigned char USB_CON; // (R/W) : $00
extern xdata unsigned char TXDAT0; // (-W-) : $XX (T0B7-T0B0)
extern xdata unsigned char TXCNT0; // (-W-) : $XX (C0B3-C0B0)
extern xdata unsigned char TXFLG0; // (R/W) : $00
extern xdata unsigned char RXDAT0; // (-R-) : $XX (R0B7-R0B0)
extern xdata unsigned char RXCNT0; // (-R-) : $XX (X0B3-X0B0)
extern xdata unsigned char RXFLG0; // (R/W) : $00
extern xdata unsigned char TXDAT1; // (-W-)
extern xdata unsigned char TXCNT1; // (-W-)
extern xdata unsigned char TXFLG1; // (R/W) : $00
#define T1EPE 0x08
#define T1SEQC 0x04
#define STAL1 0x02
#define T1FULL 0x01
extern xdata unsigned char TXFLG2; // (R/W) : $00
#define T2EPE 0x08
#define T2SEQC 0x04
#define STAL2 0x02
#define T2FULL 0x01
extern xdata unsigned char ISRC_SW; // (R/W) : $07
extern xdata unsigned char DDCPtr; // (R/W) : $07
//#define SYSREG_END TXFLG2 ; System Register end define
#endif
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