📄 bsp.c
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AT91C_BASE_PIOA->PIO_SODR = BSP_LED1;
}
break;
case 2:
if (AT91C_BASE_PIOA->PIO_ODSR & BSP_LED2) {
AT91C_BASE_PIOA->PIO_CODR = BSP_LED2;
} else {
AT91C_BASE_PIOA->PIO_SODR = BSP_LED2;
}
break;
}
}
/*
*********************************************************************************************************
* EXCEPTION HANDLER
*
* Description : This function should be used to handle any exceptions. It is called by
* OS_CPU_ARM_ExceptHndlr(), which is declared in os_cpu_a.asm
*
* Arguments : ID, an identifier used to indicate what type of ARM exception has been triggered
* Possible ID values are shown below.
* OS_CPU_ARM_EXCEPT_RESET 0x00
* OS_CPU_ARM_EXCEPT_UNDEF_INSTR 0x01
* OS_CPU_ARM_EXCEPT_SWI 0x02
* OS_CPU_ARM_EXCEPT_PREFETCH_ABORT 0x03
* OS_CPU_ARM_EXCEPT_DATA_ABORT 0x04
* OS_CPU_ARM_EXCEPT_ADDR_ABORT 0x05
* OS_CPU_ARM_EXCEPT_IRQ 0x06
* OS_CPU_ARM_EXCEPT_FIQ 0x07
*
* Notes : The ISR handler being called MUST clear the AIC by clearing any external sources and
* then writting the AIC ICCR and EOICR registers.
*********************************************************************************************************
*/
void OS_CPU_ExceptHndlr (CPU_DATA except_id)
{
BSP_FNCT_PTR pfnct;
CPU_INT32U *sp;
if (except_id == OS_CPU_ARM_EXCEPT_FIQ) {
pfnct = (BSP_FNCT_PTR)AT91C_BASE_AIC->AIC_FVR; /* Read the FIQ handler from the AIC. */
while (pfnct != (BSP_FNCT_PTR)0) { /* Make sure we don't have a NULL pointer. */
(*pfnct)(); /* Execute the handler. */
AT91C_BASE_AIC->AIC_EOICR = ~0; /* End of handler. */
pfnct = (BSP_FNCT_PTR)AT91C_BASE_AIC->AIC_FVR; /* Read the FIQ handler from the AIC. */
}
AT91C_BASE_AIC->AIC_EOICR = ~0; /* End of handler. */
} else if (except_id == OS_CPU_ARM_EXCEPT_IRQ) {
pfnct = (BSP_FNCT_PTR)AT91C_BASE_AIC->AIC_IVR; /* Read the IRQ handler from the AIC. */
while (pfnct != (BSP_FNCT_PTR)0) { /* Make sure we don't have a NULL pointer. */
(*pfnct)(); /* Execute the handler. */
AT91C_BASE_AIC->AIC_EOICR = ~0; /* End of handler. */
pfnct = (BSP_FNCT_PTR)AT91C_BASE_AIC->AIC_IVR; /* Read the IRQ handler from the AIC. */
}
AT91C_BASE_AIC->AIC_EOICR = ~0; /* End of handler. */
} else {
sp = (CPU_INT32U *)OSTCBCur->OSTCBStkPtr;
APP_TRACE_INFO(("\nCPU_ARM_EXCEPTION #%d trapped.\n", except_id));
APP_TRACE_INFO(("R0 : 0x%08x\n", *(sp + 0x01)));
APP_TRACE_INFO(("R1 : 0x%08x\n", *(sp + 0x02)));
APP_TRACE_INFO(("R2 : 0x%08x\n", *(sp + 0x03)));
APP_TRACE_INFO(("R3 : 0x%08x\n", *(sp + 0x04)));
APP_TRACE_INFO(("R4 : 0x%08x\n", *(sp + 0x05)));
APP_TRACE_INFO(("R5 : 0x%08x\n", *(sp + 0x06)));
APP_TRACE_INFO(("R6 : 0x%08x\n", *(sp + 0x07)));
APP_TRACE_INFO(("R7 : 0x%08x\n", *(sp + 0x08)));
APP_TRACE_INFO(("R8 : 0x%08x\n", *(sp + 0x09)));
APP_TRACE_INFO(("R9 : 0x%08x\n", *(sp + 0x0A)));
APP_TRACE_INFO(("R10 : 0x%08x\n", *(sp + 0x0B)));
APP_TRACE_INFO(("R11 : 0x%08x\n", *(sp + 0x0C)));
APP_TRACE_INFO(("R12 : 0x%08x\n", *(sp + 0x0D)));
APP_TRACE_INFO(("SP : 0x%08x\n", sp));
APP_TRACE_INFO(("LR : 0x%08x\n", *(sp + 0x0E)));
APP_TRACE_INFO(("PC : 0x%08x\n", *(sp + 0x0F)));
APP_TRACE_INFO(("CPSR: 0x%08x\n", *(sp + 0x00)));
/* Infinite loop on other exceptions. */
/* Should be replaced by other behavior (reboot, etc.) */
while (TRUE) {
;
}
}
}
/*
*********************************************************************************************************
* Sys_Int_Handler
*
* Description : The System Peripheral (ID = 1) may have many different devices cause interrupts under
* its ID. This functions job is to discern which event caused a System Interrupt and to
* call the correct handler(s) and process it accordingly.
*
* Arguments : none
*
* Nots : 1) At the time of this writing, both the System PIT (OSTick interrupt) and DBGU are
* initialized and use the Sys_Int_Handler.
* 2) AIC interrupts are clearned int he Sys_Int_Handler routine, the calling handler
* need only to clear its local interrupt source.
*********************************************************************************************************
*/
void Sys_Int_Handler (void)
{ /* If the PIT has reached PIV */
if ((AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) > 0) {
Tmr_TickISR_Handler(); /* Call the OSTick handler */
}
#if OS_VIEW_MODULE > 0
if (((AT91C_BASE_DBGU->DBGU_CSR & (AT91C_US_RXRDY | AT91C_US_OVRE)) > 0) ||
(((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXRDY) > 0) &&
((AT91C_BASE_DBGU->DBGU_IMR & AT91C_US_TXRDY) > 0))) {
OSView_RxTxISRHandler();
}
#endif
/* Clear System Interrupt */
AT91C_BASE_AIC->AIC_ICCR = (1 << AT91C_ID_SYS);
}
/*
*********************************************************************************************************
* TICKER INITIALIZATION
*
* Description : This function is called to initialize uC/OS-II's tick source which uses the PIT
* (typically a timer generating interrupts every 1, 10 or 100 mS).
* See OS_TICKS_PER_SEC in OS_CFG.H.
*
* Arguments : none
*********************************************************************************************************
*/
static void Tmr_TickInit (void)
{
CPU_INT32U counts;
CPU_INT32U cpu_frq;
/* Determine the number of counts per tick */
cpu_frq = BSP_MCK_Frq();
counts = (cpu_frq / (16 * OS_TICKS_PER_SEC));
/* Set the vector address for PIT */
AT91C_BASE_AIC->AIC_SVR[AT91C_ID_SYS] = (CPU_INT32U)Sys_Int_Handler;
AT91C_BASE_AIC->AIC_SMR[AT91C_ID_SYS] = AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE
| AT91C_AIC_PRIOR_LOWEST;
AT91C_BASE_AIC->AIC_ICCR = (1 << AT91C_ID_SYS);
AT91C_BASE_AIC->AIC_IECR = (1 << AT91C_ID_SYS);
/* Enable the PIT with the correct compare value */
AT91C_BASE_PITC->PITC_PIMR = AT91C_PITC_PITEN | AT91C_PITC_PITIEN | counts;
}
/*
*********************************************************************************************************
* OSView Timer Initialization
*
* Description : This function selects and initializes a timer for use with OSView and the Statistics Task
*
* Arguments : none
*********************************************************************************************************
*/
#if OS_VIEW_MODULE > 0
void OSView_TmrInit (void)
{
#if OS_VIEW_TIMER_SEL == 0
AT91C_BASE_PMC->PMC_PCER = (1 << 17); /* Enable the peripheral clk */
AT91C_BASE_TCB0->TCB_TC0.TC_CCR = (1 << 1); /* TC0 timer disabled */
AT91C_BASE_TCB0->TCB_TC0.TC_CMR &= ~(7 << 0); /* TIMER_CLOCK1 is input clk */
AT91C_BASE_TCB0->TCB_TC0.TC_CCR = (1 << 0); /* TC0 timer enabled */
AT91C_BASE_TCB0->TCB_TC0.TC_CCR = (1 << 2); /* SWTRG to reset and start */
#endif
#if OS_VIEW_TIMER_SEL == 1
AT91C_BASE_PMC->PMC_PCER = (1 << 18); /* Enable the peripheral clk */
AT91C_BASE_TCB0->TCB_TC1.TC_CCR = (1 << 1); /* TC1 timer disabled */
AT91C_BASE_TCB0->TCB_TC1.TC_CMR &= ~(7 << 0); /* TIMER_CLOCK1 is input clk */
AT91C_BASE_TCB0->TCB_TC1.TC_CCR = (1 << 0); /* TC1 timer enabled */
AT91C_BASE_TCB0->TCB_TC1.TC_CCR = (1 << 2); /* SWTRG to reset and start */
#endif
#if OS_VIEW_TIMER_SEL == 2
AT91C_BASE_PMC->PMC_PCER = (1 << 19); /* Enable the peripheral clk */
AT91C_BASE_TCB0->TCB_TC2.TC_CCR = (1 << 1); /* TC2 timer disabled */
AT91C_BASE_TCB0->TCB_TC2.TC_CMR &= ~(7 << 0); /* TIMER_CLOCK1 is input clk */
AT91C_BASE_TCB0->TCB_TC2.TC_CCR = (1 << 0); /* TC2 timer enabled */
AT91C_BASE_TCB0->TCB_TC2.TC_CCR = (1 << 2); /* SWTRG to reset and start */
#endif
}
#endif
/*
*********************************************************************************************************
* READ TIMER FOR uC/OS-View
*
* Description : This function is called to read the current counts of a 16 bit free running timer.
* This value is then used to compute CPU usage in uC/OS-View.
*
* Arguments : none
*
* Returns ; The 16 bit count (in a 32 bit variable) of the timer assuming the timer is an UP counter.
*********************************************************************************************************
*/
#if OS_VIEW_MODULE > 0
CPU_INT32U OSView_TmrRd (void)
{
CPU_INT32U cnts;
#if OS_VIEW_TIMER_SEL == 0
cnts = (CPU_INT32U)(AT91C_BASE_TCB0->TCB_TC0.TC_CV & 0x0000FFFF); /* Read timer 0 */
#endif
#if OS_VIEW_TIMER_SEL == 1
cnts = (CPU_INT32U)(AT91C_BASE_TCB0->TCB_TC1.TC_CV & 0x0000FFFF); /* Read timer 1 */
#endif
#if OS_VIEW_TIMER_SEL == 2
cnts = (CPU_INT32U)(AT91C_BASE_TCB0->TCB_TC2.TC_CV & 0x0000FFFF); /* Read timer 2 */
#endif
return (cnts);
}
#endif
/*
*********************************************************************************************************
* PIT IRQ HANDLER
*
* Description : This function handles the PIT interrupt that is used to generate TICKs for uC/OS-II.
*
* Arguments : none
*
* Notes : The AIC interrupts are cleared in the calling Sys_Int_Handler function since the System
* interrupt is multiplexed with several devices such as the PIT which drives the OS Ticker.
*********************************************************************************************************
*/
static void Tmr_TickISR_Handler (void)
{
CPU_INT32U status;
/* Clear the PIT interrupt */
status = AT91C_BASE_PITC->PITC_PIVR;
(void)status; /* Prevent a compiler warning that status was never used */
OSTimeTick(); /* Tell uC/OS-II about clock tick */
}
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